• 산업기술연구
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• 제43권1호
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• pp.49-55
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• 2023

Cluster tools are extensively employed in various wafer fabrication processes within the semiconductor manufacturing industry, including photo lithography, etching, and chemical vapor deposition. Contemporary fabrication facilities encounter customer orders with technical specifications that are similar yet slightly varied. Consequently, modern fabrications concurrently manufacture two or three different wafer types using a cluster tool to maximize chamber utilization and streamline the flow of wafer lots between different process stages. In this review, we introduce two methods of concurrent processing of multiple wafer types: 1) concurrent processing of multiple wafer types with different job flows, 2) concurrent processing of multiple wafer types with identical job flows. We describe relevant research trends and achievements and discuss future research directions.

• 설비공학논문집
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• 제16권5호
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• pp.475-481
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• 2004

This paper presents a force model of the clean tube system, which was developed as a means of transferring air-floated wafers inside a closed tube filled with super clean air. The recovering force from the holes for floating wafers is modeled as a linear spring and thus the wafers motion is modeled as a mass-spring-damper system. The propelling forces are modeled as linear along with the wafer location. The paper also proposes a control method to emit and stop a wafer at the center of a control unit. It reveals the minimum value of the propelling force to leave from the control unit. In order to stop the wafer, it utilizes the exact time when the wafer arrives at the position to activate the propelling force. Experiments with the clean tube system built for the 12 inch wafer shows the validity of the proposed model and the algorithm.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2002년도 춘계학술대회 논문집
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• pp.42-45
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• 2002

General wheel mark in mono-crystalline silicon wafer finding is able to be expected because it depends on radius ratio and angular velocity ratio of wafer and wheel. The pattern is predominantly determined by the contour of abrasive grits resulting from a relative motion. Although such a wheel mark is made uniform pattern if the process parameters are fixed, sub-surface defect is expected to be distributed non-uniformly because of characteristic of mono-crystalline silicon wafer that has diamond cubic crystal. Consequently it is considered that this phenomenon affects the following process. This paper focused on kinematic analysis of wafer grinding process and simulation program was developed to verify the effect of process variables on wheel mark. And finally, we were able to predict sub-surface defect distribution that considered characteristic of mono-crystalline silicon wafer

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2003년도 춘계학술대회 논문집
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• pp.459-462
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• 2003

This paper presents a force model of the clean tube system, which was developed as a means for transferring the air-floated wafers inside the closed tube filled with the super clean air. The recovering force from the holes for floating wafers is modeled as a linear spring and thus the wafer motion is modeled as a mass-spring-damper system. The propelling forces are modeled as linear along with the wafer location. The paper also proposes the control method to emit and stop a wafer at the center of a control unit. It shows the minimum value of the propelling force to leave from the control unit. In order to stop the wafer, it utilizes the exact time when a wafer arrives at the position to activate the propelling force. Experiments with the clean tube system built for 12 inch wafer shows the validity of the proposed model and the algorithm.

• 반도체디스플레이기술학회지
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• 제19권2호
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• pp.77-81
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• 2020

Silicon wafer etching in micro electro mechanical systems (MEMS) fabrication is challenging to form 3-D structures. Well known Si-wet etch of silicon employs potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH) and sodium hydroxide (NaOH). However, the existing silicon wet etching process has a fatal disadvantage that etching of the back side of the wafer is hard to avoid. In this study, a wet etching bath for 150 mm wafers was designed to prevent back-side etching of silicon wafer, and we demonstrated the optimized process recipe to have anisotropic wet etching of silicon wafer without any damage on the backside. We also presented the design of wet bath for 300 mm wafer processing as a promising process development.

• 반도체디스플레이기술학회지
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• 제21권1호
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• pp.62-66
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• 2022

Semiconductor is one of the most internationally competitive areas among domestic industries, the major concern of which is the stability of the wafer manufacturing processes. The packaging process is the final step in wafer manufacturing. Problems in the wafer packaging process cause large losses. The vibrations are supposed to be the most important factors for the packaging quality. In this study, the structure of a packaging box was analyzed through experiments and computer simulations, and further the effects of design alterations to suppress the vibrations have been investigated. The final result shows that the vibrations can be reduced substantially to improve the stability of the structure.

• 한국재료학회지
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• 제24권12호
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• pp.682-688
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• 2014

Physical and chemical changes in a polished wafer and in $2.5{\mu}m$ & $4{\mu}m$ epitaxially grown Si layer wafers (Epilayer wafer) after surface treatment were investigated. We characterized the influence of surface treatment on wafer properties such as surface roughness and the chemical composition and bonds. After each surface treatment, the physical change of the wafer surface was evaluated by atomic force microscopy to confirm the surface morphology and roughness. In addition, chemical changes in the wafer surface were studied by X-ray photoemission spectroscopy measurement. Changes in the chemical composition were confirmed before and after the surface treatment. By combined analysis of the physical and chemical changes, we found that diluted hydrofluoric acid treatment is more effective than buffered oxide etching for $SiO_2$ removal in both polished and Epi-Layer wafers; however, the etch rate and the surface roughness in the given treatment are different among the polished $2.5{\mu}m$ and $4{\mu}m$ Epi-layer wafers in spite of the identical bulk structural properties of these wafers. This study therefore suggests that independent surface treatment optimization is required for each wafer type, $2.5{\mu}m$ and $4{\mu}m$, due to the meaningful differences in the initial surface chemical and physical properties.

• 한국기계가공학회지
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• 제19권3호
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• pp.22-28
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• 2020

This paper investigates the effects of retaining ring materials, particularly PPS and PEEK, used in the CMP process, on wafer polishing and ring wear. CMP can be performed using bonded type retaining rings made with PPS or injection molding type retaining rings made with PEEK. In this study, after polishing a wafer with a PPS retaining ring, the average profile height of the wafer was 0.098 ㎛ less than that of the wafer polished with a PEEK retaining ring, implying that PPS retaining rings achieve a higher polishing rate. In addition, the center area of the wafer profile had less deviation and improved flatness after polishing with the PPS ring. These results indicate that a higher polishing rate and smaller profile height deviation can be achieved using retaining rings made with PPS compared to retaining rings made with PEEK. Therefore, with semiconductor circuit patterns becoming finer and wafer sizes becoming larger, the use of PPS in CMP retaining rings can obtain more stable wafer polishing results compared to that of PEEK.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.629-632
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• 1998

This paper presents a new and simple technique to realize high Q inductor on low resistivity silicon wafer with 6 $\Omega$.cm. This technique is very compatible with bipolar and CMOS standard silicon process. By forming the deep and narrow trenches on the low resistivity wafer substrate under inductor pattern, oxidizing and filling with undoped polysilicon, the low resistivity silicon wafer acts as high resistivity wafer being suitable for the fabrication of high Q inductor. By using this technique the quality factor (Q) for 8-turn spiral inductor was improved up to max. 10.3 at 2 ㎓ with 3.0 $\mu\textrm{m}$ of metal thickness. The experiment results show that Q on low resistivity silicon wafer with the trench technique have been improved more than 2 times compared to the conventional low resistivity silicon wafer without trenches.

• 한국재료학회지
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• 제17권7호
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• pp.347-351
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• 2007

Vertical interconnect technology called 3D stacking has been a major focus of the next generation of IC industries. 3D stacked devices in the vertical dimension give several important advantages over conventional two-dimensional scaling. The most eminent advantage is its performance improvement. Vertical device stacking enhances a performance such as inter-die bandwidth improvements, RC delay mitigation and geometrical routing and placement advantages. At present memory stacking options are of great interest to many industries and research institutes. However, these options are more focused on a form factor reduction rather than the high performance improvements. In order to improve a stacked device performance significantly vertical interconnect technology with wafer level stacking needs to be much more progressed with reduction in inter-wafer pitch and increases in the number of stacked layers. Even though 3D wafer level stacking technology offers many opportunities both in the short term and long term, the full performance benefits of 3D wafer level stacking require technological developments beyond simply the wafer stacking technology itself.