• 한국생산제조학회지
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• 제22권1호
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• pp.168-172
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• 2013

In 3D wafer-stacking technology, one of the major issues is wafer warpage. Especially, The important reason of warpage has been known due to CTE(Coefficient of Thermal Expansion) mismatch between materials. It was too hard to choose how to make the FE model for blanket structured wafer level 3D packaging, because the thickness of each layer in wafer level 3D packaging was too small (micro meter or nano meter scale) comparing with diameter of wafer (6 or 8 inches). In this study, the FE model using the shell element was selected and simulated by the ANSYS WorkBench to investigate effects of the CTE on the warpage. To verify the FE model, it was compared by experimental results.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 춘계학술대회 논문집 유기절연재료 전자세라믹 방전플라즈마 일렉트렛트 및 응용기술
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• pp.223-227
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• 2002

As the channel length of device shrinks below $0.13{\mu}m$, CMP(chemical mechanical polishing) process got into key process for global planarization in the chip manufacturing process. The removal rate and non-uniformity of the CMP characteristics occupy an important position to CMP process control. Especially, the post-CMP thickness variation depends on the device yield as well as the stability of subsequent process. In this paper, every wafer polished two times for the improvement of oxide CMP process characteristics. Then, we discussed the removal rate and non-uniformity characteristics of post-CMP process. As a result of CMP experiment, we have obtained within-wafer non-uniformity (WIWNU) below 4 [%], and wafer-to-wafer non-uniformity (WTWNU) within 3.5 [%]. It is very good result, because the reliable non-uniformity of CMP process is within 5 [%].

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.323-323
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• 2010

Saw damage of crystalline silicon wafer is unavoidable factor. Usually, alkali treatment for removing the damage has been carried out as the saw damage removal (SDR) process for priming the alkali texture. It usually takes lots of time and energy to remove the sawed damages for solar grade crystalline silicon wafers We implemented two different mixed acidic solution treatments to obtain the improved surface structure of silicon wafer without much sacrifice of the silicon wafer thickness. At the first step, the silicon wafer was dipped into the mixed acidic solution of $HF:HNO_3$=1:2 ration for polished surface and at the second step, it was dipped into the diluted mixed acidic solution of $HF:HNO_3:H_2O$=7:3:10 ratio for porous structure. This double treatment to the silicon wafer brought lower reflectance (25% to 6%) and longer carrier lifetime ($0.15\;{\mu}s$ to $0.39\;{\mu}s$) comparing to the bare poly-crystalline silicon wafer. With optimizing the concentration ratio and the dilution ratio, we can not only effectively substitute the time consuming process of SDR to some extent but also skip plasma enhanced chemical vapor deposition (PECVD) process. Moreover, to conduct alkali texture for pyramidal structure on silicon wafer surface, we can use only nitric acid rich solution of the mixed acidic solution treatment instead of implementing SDR.

• 한국재료학회지
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• 제23권1호
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• pp.35-40
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• 2013

In this study, the influence on the surface passivation properties of crystalline silicon according to silicon wafer thickness, and the correlation with a-Si:H/c-Si heterojunction solar cell performances were investigated. The wafers passivated by p(n)-doped a-Si:H layers show poor passivation properties because of the doping elements, such as boron(B) and phosphorous(P), which result in a low minority carrier lifetime (MCLT). A decrease in open circuit voltage ($V_{oc}$) was observed when the wafer thickness was thinned from $170{\mu}m$ to $50{\mu}m$. On the other hand, wafers incorporating intrinsic (i) a-Si:H as a passivation layer showed high quality passivation of a-Si:H/c-Si. The implied $V_{oc}$ of the ITO/p a-Si:H/i a-Si:H/n c-Si wafer/i a-Si:H/n a-Si:H/ITO stacked layers was 0.715 V for $50{\mu}m$ c-Si substrate, and 0.704 V for $170{\mu}m$ c-Si. The $V_{oc}$ in the heterojunction solar cells increased with decreases in the substrate thickness. The high quality passivation property on the c-Si led to an increasing of $V_{oc}$ in the thinner wafer. Short circuit current decreased as the substrate became thinner because of the low optical absorption for long wavelength light. In this paper, we show that high quality passivation of c-Si plays a role in heterojunction solar cells and is important in the development of thinner wafer technology.

• 한국태양에너지학회 논문집
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• 제39권3호
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• pp.9-17
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• 2019

Laser cutting cell of solar cells can achieve high voltage and efficiency through more array than conventional 6 inch cell compared to same area. In this study, we fabricated c-Si cutting cell with various lasers and laser conditions such as power, speed, and number of times. In the case of picosecond laser, excellent surface characteristics were obtained due to small surface defects and low thermal damage at the output of 20W and the speed of 100 mm/s. However, it is not possible to fabricate a cutting cell having good characteristics due to nonuniform cutting inside the wafer when the processing for forming a cutting cell is not sufficiently performed. For nanosecond lasers, the best wafer characteristics were obtained for fabrication of excellent cutting cells at a frequency of 500 kHz and a laser speed of 100 mm/s. However, the nanosecond laser has not been processed sufficiently in the condition of a number of times. As a result, it was confirmed that the wafer thickness was cut by $63{\mu}m$ of the cell thickness of $170{\mu}m$ in the condition of five times of laser process. It was found that more than 30% of the wafer thickness had to be processed to fabricate the cutting cell. After cutting the 6-inch cell having the voltage of 0.65 V, we obtained the voltage of about 0.63 V.

• 한국결정학회:학술대회논문집
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• 한국결정학회 2001년도 정기총회 및 춘계학술대회연구발표회(한국결정학회)
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• pp.23-23
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• 2001

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2009년도 춘계학술대회 논문집
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• pp.249-250
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• 2009

• 전기전자학회논문지
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• 제22권2호
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• pp.427-431
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• 2018

본 논문에서는 최근 전력반도체 산업에서 활용되어지는 와이드밴드갭 반도체 중에 하나인 $Ga_2O_3$를 이용한 에피웨이퍼 성장에 관련되어 서술하였다. GaN 성장시 활용되어지는 HVPE법을 이용하여 Sn이 도핑된 $Ga_2O_3$ 기판웨이퍼에 평균 $5.3{\mu}m$ 두께로 성장시켰다. 일반적으로 화합물반도체의 에피 두께가 $5{\mu}m$일 경우 SiC의 경우 600V 전력반도체소자를 제작할 수 있으며, $Ga_2O_3$ 에피웨이퍼의 경우에는 1000V이상의 전력소자를 제작할 수 있다. 성장된 에피웨이퍼의 J-V 측정 결과 $2.9-7.7m{\Omega}{\cdot}cm^2$의 온저항을 얻을 수 있었으며, 역방향의 경우 상당히 높은 전압에서도 누설전류가 거의 없음을 알 수 있었다.

• Composites Research
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• 제20권5호
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• pp.49-55
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• 2007

반도체 쿼츠 웨이퍼 다이싱용 블레이드는 마이크로/나노 디바이스와 부품을 제조하기 위해 고정밀도의 가공성을 요구한다. 따라서 균일한 마이크로/나노 선폭의 가공을 위해서는 블레이드의 제작 단계에서 균일한 두께와 밀도를 유지하는 것이 중요하다. 기존의 실리콘웨이퍼 가공을 위해서는 금속의 블레이드가 사용되고 있지만 쿼츠 웨이퍼 가공을 위해서는 고분자 복합재가 사용된다. 이러한 복합재는 가공성, 전기전도성, 그리고 적절한 강도와 연성 및 마모저항성이 있어야 한다. 그러나 기존의 건식성형 공정으로는 균일성을 유지하기 위해 많은 공정과 비용이 소비되고 있다. 본 연구에서는 도전성 나노 세라믹스 분말, 연마재 세라믹스 분말에 열경화성 수지, 전도성 고분자를 혼합한 복합재 분말을 습식성형 공정에 의해 제조, 평가하는 연구를 수행하였다. 먼저 복합재 분말을 액상과 혼합하여 블레이드를 제작하였으며, 액상의 종류, 액상 건조공정의 영향을 고찰하였다. 평가는 마이크로미터 측정기와 현미경을 이용하여 두께를 측정하였다. 두께편차와 기공률, 밀도, 경도, 등의 특성을 비교, 평가하였다. 그 결과 습식성형에 의해 블레이드의 두께편차를 감소시킬 수 있었으며, 경도 등의 특성을 향상시킬 수 있었다.

• Tribology and Lubricants
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• 제18권4호
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• pp.260-266
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• 2002

In this study, the effects of oxide layer farmed on the wear tracks of TiN coated silicon wafer on friction and wear characteristics were investigated. Silicon wafer was used for the substrate of coated disk specimens, which were prepared by depositing TiN coating with 1 ${\mu}{\textrm}{m}$ in coating thickness. AISI 52100 steel ball was used fur the counterpart. The tests were performed both in air for forming oxide layer on the wear track and in nitrogen to avoid oxidation. This paper reports characterization of the oxide layer effects on friction and wear characteristics using X-ray diffraction(XRD), Auger electron spectroscopy(AES), scanning electron microscopy (SEM) and multi-mode atomic force microscope(AFM).