• 제목/요약/키워드: Wafer temperature uniformity

검색결과 74건 처리시간 0.03초

하중 혼합감도함수를 이용한 RTP 시스템의 견실제어기 설계 (Robust controller design for RTP system using weighted mixed sensitivity minimization)

  • 이상경;오도창;박홍배
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 1997년도 한국자동제어학술회의논문집; 한국전력공사 서울연수원; 17-18 Oct. 1997
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    • pp.434-437
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    • 1997
  • In this paper, we present an $H^{\infty}$ controller design of RTP system satisfying robust stability and performance using weighted mixed sensitivity minimization. In industrial fields, RTP system is widely used for improving the oxidation and the annealing in semiconductor manufacturing process. The main control factors are temperature control of wafer and uniformity in the wafer. The control of temperature and uniformity has been solved by PI control method. We improve robust stability and performance of RTP system by the design of $H^{\infty}$ controller using the weighted mixed sensivity function. An example is proposed to show the validity of proposed method.d.

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LTP 퍼니스의 내부 유동 및 온도 균일도 최적화를 위한 실천공학교육적 문제해결 (Problem Solving about Practical Engineering Education based on Analysis on Optimized Internal Flow of LTP Furnace and Uniformity of Temperature)

  • 김진우;윤기만;조은정
    • 실천공학교육논문지
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    • 제10권2호
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    • pp.125-129
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    • 2018
  • 이 논문은 LTP 퍼니스의 최적화 된 내부 유동과 온도의 균일성에 대한 수치 해석에 관한 것이다. 반도체 제조 공정에서 실리콘 웨이퍼를 어닐링하기 위한 기능을 수행한다. 특히 챔버 내부의 최고 온도를 약 $400^{\circ}C$의 고온으로 유지하여 웨이퍼를 보강한다. 공정이 고온에서 완료되면 열 교환기를 통해 온도를 낮추고 이를 수행하기 위한 작업이 반복된다. 이 논문에서 최종적인 목표는 LTPS 퍼니스의 유동 해석을 통해 챔버의 단열 공급과 배기 구조의 최적 설계를 도출하는 것과 교육과정 개발을 위한 사례 발굴에 있다.

Membrane Embedded Polisher Head의 Plate 구조의 영향 (The Influence of Plate Structure in Membrane Embedded Head Polisher)

  • 조경수;이양원;김대영;이진규;김활표;정제덕;하현우;정호석;양원식
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2004년도 추계학술대회 논문집 Vol.17
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    • pp.136-139
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    • 2004
  • The requirement of planarity, such as with-in-wafer nonuniformity, post thickness range, have become increasingly stringent as critical dimensions of devices are decreased and a better control of a planarity become important. The key factors influencing the planarity capability of the CMP process have been well understood through numerous related experiments. These usually include parameters such as process pressures, relative velocities, slurry temperature, polishing pad materials and polishing head structure. Many study have been done about polishing pad and its groove structure because it's considered as one of the key factors which can decide wafer uniformity directly. But, not many study have been done about polisher head structure, especially about polisher head plate design. The purpose of this paper is to know how the plate structure can affect wafer uniformity and how to deteriorate wafer yield. Furthermore, we studied several new designed plate to improve wafer uniformity and also improve wafer yield.

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Hot Plate 신뢰성 시험.평가시스템 개발 (Reliability Evaluation System of Hot Plate for Photoresist Baking)

  • 송준엽;송창규;노승국;박화영
    • 한국정밀공학회지
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    • 제19권8호
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    • pp.180-186
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    • 2002
  • Hot Plate is the major unit that it used to remove damp of wafer surface, to strength adhesion of photoresist (PR) and to bake coated PR in FAB process of semiconductor. The badness of Hot Plate (HP) has directly influence upon the performance of wafer, it is necessary to guarantee the performance of HP. In this study, a reliability evaluation system has been designed and developed, which is to measure and to estimate thermal uniformity and flatness of HP in range of temperature 0~$250^\circC$. This system has included the techniques which measures and analyzes thermal uniformity using infrared thermal vision, and which compensates measuring error of flatness using laser displacement sensor For measuring flatness, a measurement stage of 3 axes are developed which adapts the precision encoder. The allowable error of this system in respect of thermal uniformity is less $than\pm0.1^\circC$ and in respect of flatness is less $than\pm$1mm . It is expected that the developed system can measure from $\Phi200mm\;(wafer 8")\;to\;\Phi300mm$ (wafer 12") and also can be used in performance test of the Cool Plate and industrial heater, etc.

Adhesive bonding using thick polymer film of SU-8 photoresist for wafer level package

  • Na, Kyoung-Hwan;Kim, Ill-Hwan;Lee, Eun-Sung;Kim, Hyeon-Cheol;Chun, Kuk-Jin
    • 센서학회지
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    • 제16권5호
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    • pp.325-330
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    • 2007
  • For the application to optic devices, wafer level package including spacer with particular thickness according to optical design could be required. In these cases, the uniformity of spacer thickness is important for bonding strength and optical performance. Packaging process has to be performed at low temperature in order to prevent damage to devices fabricated before packaging. And if photosensitive material is used as spacer layer, size and shape of pattern and thickness of spacer can be easily controlled. This paper presents polymer bonding using thick, uniform and patterned spacing layer of SU-8 2100 photoresist for wafer level package. SU-8, negative photoresist, can be coated uniformly by spin coater and it is cured at $95^{\circ}C$ and bonded well near the temperature. It can be bonded to silicon well, patterned with high aspect ratio and easy to form thick layer due to its high viscosity. It is also mechanically strong, chemically resistive and thermally stable. But adhesion of SU-8 to glass is poor, and in the case of forming thick layer, SU-8 layer leans from the perpendicular due to imbalance to gravity. To solve leaning problem, the wafer rotating system was introduced. Imbalance to gravity of thick layer was cancelled out through rotating wafer during curing time. And depositing additional layer of gold onto glass could improve adhesion strength of SU-8 to glass. Conclusively, we established the coating condition for forming patterned SU-8 layer with $400{\mu}m$ of thickness and 3.25 % of uniformity through single coating. Also we improved tensile strength from hundreds kPa to maximum 9.43 MPa through depositing gold layer onto glass substrate.

고속 열처리공정 시스템에서의 웨이퍼 상의 온도분포 추정 (Estimation of Temperature Distribution on Wafer Surface in Rapid Thermal Processing Systems)

  • 이석주;심영태;고택범;우광방
    • 제어로봇시스템학회논문지
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    • 제5권4호
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    • pp.481-488
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    • 1999
  • A thermal model based on the chamber geometry of the industry-standard AST SHS200MA rapid thermal processing system has been developed for the study of thermal uniformity and process repeatability thermal model combines radiation energy transfer directly from the tungsten-halogen lamps and the steady-state thermal conducting equations. Because of the difficulties of solving partial differential equation, calculation of wafer temperature was performed by using finite-difference approximation. The proposed thermal model was verified via titanium silicidation experiments. As a result, we can conclude that the thermal model show good estimation of wafer surface temperature distribution.

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정전척 온도분포 개선을 위한 냉각수 관로 형상 (Coolant Path Geometry for Improved Electrostatic Chuck Temperature Variation)

  • 이기석
    • 반도체디스플레이기술학회지
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    • 제10권4호
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    • pp.21-23
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    • 2011
  • Uniformity of plasma etching processes critically depends on the wafer temperature and its distribution. The wafer temperature is affected by plasma, chucking force, He back side pressure and the surface temperature of ESC(electrostatic chuck). In this work, 3D mathematical modeling is used to investigate the influence of the geometry of coolant path and the temperature distribution of the ESC surface. The model that has the coolant path with less change of the cross-sectional area and the curvature shows low standard deviation of the ESC surface temperature distribution than the model with the coolant path of the larger surface area and more geometric change.

Si-adhesive 층의 불량에 따른 정전척 온도분포 (Effect of the Si-adhesive layer defects on the temperature distribution of electrostatic chuck)

  • 이기석
    • 반도체디스플레이기술학회지
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    • 제11권2호
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    • pp.71-74
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    • 2012
  • Uniformity of the wafer temperature is one of the important factors in etching process. Plasma, chucking force, backside helium pressure and the surface temperature of ESC(electrostatic chuck) affect the wafer temperature. ESC consists of several layers of structure. Each layer has own thermal resistance and the Si-adhesive layer has highest thermal resistance among them. In this work, the temperature distribution of ESC was analyzed by 3-D FEM with various defects and the thickness deviation of the Si-adhesive layer. The result with Si-adhesive layer with the low center thickness deviation shows modified temperature distribution of ESC surface.

Photoreflectance study of stress in GaAs/Si structure

  • S. W. ppark;Kim, J.W.;pp.W.Yu
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 1998년도 제14회 학술발표회 논문개요집
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    • pp.114-115
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    • 1998
  • Photoreflectance (pR) measurement h have been employed to study the uniformity of G GaAs!Si 3" wafer. The PR shows the energy of l light and heavy hole even at room temperature. F From the observed energy of LH and HH, it can b be seen that the center of the wafer is more s stressed than the 뼈ge. On the basis of biaxial t tensile stress the higher and lower. transitions are a attributed to heavy and light hole respectively.vely.

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부분 가열을 이용한 저온 Hermetic 패키징 (Low Temperature Hermetic Packaging using Localized Beating)

  • 심영대;김영일;신규호;좌성훈;문창렬;김용준
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 2002년도 추계학술대회 논문집
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    • pp.1033-1036
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    • 2002
  • Wafer bonding methods such as fusion and anodic bonding suffer from high temperature treatment, long processing time, and possible damage to the micro-scale sensor or actuators. In the localized bonding process, beating was conducted locally while the whole wafer is maintained at a relatively low temperature. But previous research of localized heating has some problems, such as non-uniform soldering due to non-uniform heating and micro crack formation on the glass capsule by thermal stress effect. To address this non-uniformity problem, a new heater configuration is being proposed. By keeping several points on the heater strip at calculated and constant potential, more uniform heating, hence more reliable wafer bonding could be achieved. The proposed scheme has been successfully demonstrated, and the result shows that it will be very useful in hermetic packaging. Less than 0.2 ㎫ contact Pressure were used for bonding with 150 ㎃ current input for 50${\mu}{\textrm}{m}$ width, 2${\mu}{\textrm}{m}$ height and 8mm $\times$ 8mm, 5mm$\times$5mm, 3mm $\times$ 3mm sized phosphorus-doped poly-silicon micro heater. The temperature can be raised at the bonding region to 80$0^{\circ}C$, and it was enough to achieve a strong and reliable bonding in 3minutes. The IR camera test results show improved uniformity in heat distribution compared with conventional micro heaters. For gross leak check, IPA (Isopropanol Alcohol) was used. Since IPA has better wetability than water, it can easily penetrate small openings, and is more suitable for gross leak check. The pass ratio of bonded dies was 70%, for conventional localized heating, and 85% for newly developed FP scheme. The bonding strength was more than 30㎫ for FP scheme packaging, which shows that FP scheme can be a good candidate for micro scale hermetic packaging.

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