• Transactions of the Korean Society of Mechanical Engineers
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• v.18 no.1
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• pp.175-183
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• 1994

To investigate thermophoretic effect on particle deposition, average deposition velocity toward a horizontal wafer surface in vertical airflow is measured keeping the wafer surface temperature different from the surrounding air temperature. In the present measurement, the temperature difference is maintained in the range from -10 to $4^{\circ}$ C Polystyrene latex (PSL) spheres of diameter between 0.3 and 0.8 .mu.m are used for the experiment. The number of particles deposited on a wafer surface is estimated from the measurements using a wafer surface scanner (PMS SAS-3600). Experimental data are compared with prediction model results.

• Journal of the Semiconductor & Display Technology
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• v.11 no.2
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• pp.63-69
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• 2012

As decreasing size of chips, the need of wafer level packaging is increased in semi-conductor and display industries. Temperature uniformity is a crucial factor in vacuum soldering process to guarantee quality of bonding between chips and wafer. In this paper, a stepwise iterative algorithm has been suggested to obtain output profile of each heat source. Since this algorithm is based on open-loop stepwise iterative experimental technique, it is easier to implement and cost effective than real time feedback controls. Along with some experiments, it was shown that the suggested algorithm can remarkably improve temperature uniformity of wafer during whole heating process compared with the ordinary manual trial-and error method.

• Proceedings of the KIEE Conference
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• 1992.07b
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• pp.850-853
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• 1992

A cryogenic electron cyclotron resonance plasma etching system has been built to study wafer-temperature in the silicon etching characteristics. The wafer temperature was controlled from -150 to +30 $^{\circ}C$ during etching using the liquid nitrogen cooled helium gas. Although silicon was etched isotropically in $SF_6$ plasma at room temperatures, we found that it is possible to suppress the etch undercut in Si by reducing a substrate temperature without side wall passivation. In addition, the selectivity of silicon to photoresist was improved considerably at a low wafer temperature. Etch rates, anisotropy and selectivity to photo resist are measured as a function of the wafer temperature in the region of -125 $\sim$ 25$^{\circ}C$ and rf bias power of 20W $\sim$ 80W.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.11 no.1
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• pp.26-32
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• 2012

Polishing is one of the important methods in manufacturing of Si wafers and in thinning of completed device wafers. This study will report the characteristic of wafer according to processing time, machining speed and pressure which have major influence on the abrasion of Si wafer polishing. It is possible to evaluation of wafer abrasion by load cell and infrared temperature sensor. The characteristic of wafer surface according to processing condition is selected to use a result data that measure a pressure, machining speed, and the processing time. This result is appeared by the characteristic of wafer surface in machining condition. Through that, the study cans evaluation a wafer characteristic in variable machining condition. It is important to obtain optimal condition. Thus the optimum condition selection of ultra precision Si wafer polishing using load cell and infrared temperature sensor. To evaluate each machining factor, use a data through each sensor. That evaluation of abrasion according to variety condition is selected to use a result data that measure a pressure, machining speed, and the processing time. And optimum condition is selected by this result.

• Journal of Institute of Control, Robotics and Systems
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• v.6 no.9
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• pp.831-835
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• 2000

The uniformity of themperature on a wafer is a wafer is one the most important parameters to conterol the RTF(Rapid Thermal Process) with proper input signals. It is impossible to achieve the uniformity of temperature without the exact estimation of temperature ar all points on the wafer. There fore, it is difficult to understand the internal dynamics as well as the structural complexities of the RTP, which is aprimary obstacle to measure the distributed temperatures on the wafer accurately. Furthermore, it is also hard to accomplish desirable estimation because only a few pyrometers are available in the general equipments. In the paper, a thermal model based on the chamber grometry of the AST SHS200 RTP system is developed to effectively control the thermal uniformity on the wafer. First of all, the estimation method of one-point measurement is developed, which is properly extended to the case of multi-point measurements. This thermal model is validated through simulation and experiments. The proposed work can be utilized to building a run-by -run or a real-time control of the RTP.

• Journal of the Korean Ceramic Society
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• v.28 no.6
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• pp.495-501
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• 1991

This study is intended to make defect-free region, denuded zone at the silicon wafer surface for semiconductor device substrates. In this experiment, initial oxygen concentration of starting material CZ-grown silicon wafer, various heat treatment combinations, denuding ambient and the amounts of oxygen reduction were measured, and then denuded zone (DZ) formation and depth were investigated. In Low/High anneal (DZ formation could be achieved), the optimum temperature for Low anneal was 700$^{\circ}C$∼750$^{\circ}C$. In case of High anneal, with the time increased, DZ depth was increased at 1000$^{\circ}C$, 1150$^{\circ}C$ respectively, but on the contrary, DZ depth was decreased at low temperature 900$^{\circ}C$. As well, out-diffusion time below 2 hours was unsuitable for effective Gettering technique even though the temperature was high, and DZ formation could be achieved when initial oxygen concentration was only above 14 ppm in silicon wafer.

• Journal of the Semiconductor & Display Technology
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• v.19 no.2
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• pp.16-21
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• 2020

How accurately reproducible energy is delivered to the wafer in the process of making thin films using PE-CVD (Plasma enhanced chemical vapor deposition) during the semiconductor process. This is the most important technique, and most of the reaction on the wafer surface is made by thermal energy. In this study, we studied the method of monitoring the change of thermal energy transferred to the wafer surface by monitoring the temperature change according to the change of the thin film formed on the showerhead facing the wafer. Through this research, we could confirm the monitoring of wafer thin-film which is changed due to abnormal operation and accumulation of equipment, and we can expect improvement of semiconductor quality and yield through process reproducibility and equipment status by real-time monitoring of problem of deposition process equipment performance.

• Journal of the Semiconductor & Display Technology
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• v.23 no.2
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• pp.55-59
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• 2024

Plasma Enhanced Chemical Vapor Deposition (PE-CVD) is a widely used technology in semiconductor manufacturing for thin film deposition. The implementation of wafer guide rings in PE-CVD processes is crucial for enhancing efficiency and product quality by ensuring uniform deposition around wafer edges and reducing particle generation. On the other hand, to prevent overall temperature non-uniformity and degradation of thin film quality within the chamber, it is essential to consider various parameters comprehensively. In this study, after applying the wafer guide rings, temperature variations and fluid flow changes were simulated. Additionally, by simulating the temperature and flow changes when applied to the PE-CVD chamber, this paper discusses the importance of optimizing variables within the entire chamber.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.2
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• pp.62-67
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• 2000

The uniformity of temperature on a wafer is one of the most important parameters to control the RTP (Rapid Thermal Process) with proper input signals. Since it is impossible to achieve the uniformity of temperature without exact estimation of temperature at all points on the wafer, the difficulty of understanding internal dynamics and structural complexities of the RTP is a primary obstacle to accurately measure the distributed temperatures on the wafer. Furthermore, it is also hard to accomplish desirable estimation because only few pyrometers have been commonly available in the general equipments. In the paper, a thermal model based on the chamber geometry of the AST SHS200 RTP system is developed to effectively control the thermal uniformity on the wafer. First of all, the estimation method of one-point measurement is developed, which is properly extended to the case of multi-point measurements. This thermal model is validated through certain simulation and experiments. The work can be usefully contributed to building a run-by-run or a real-time controls of the RTP.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.10
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• pp.451-457
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• 2003

The silicon wafer is stable status at room temperature, but it is weak at high temperatures which is necessary for it to be fabricated into a power semiconductor device. During thermal diffusion processing, a high temperature produces a variety thermal stress to the wafer, resulting in device failure mode which can cause unwanted oxide charge or some defect. This disrupts the silicon crystal structure and permanently degrades the electrical and physical characteristics of the wafer. In this paper, the electrical characteristics of a single oxide layer due to high temperature diffusion process, wafer resistivity and thickness of polyback was researched. The oxide quality was examined through capacitance-voltage characteristics, defect density and BMD(Bulk Micro Defect) density. It will describe the capacitance-voltage characteristics of the single oxide layer by semiconductor process and device simulation.