• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1988년도 한국자동제어학술회의논문집(국내학술편); 한국전력공사연수원, 서울; 21-22 Oct. 1988
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• pp.353-359
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• 1988

In this paper, the design and implementation of a multi-processor based die bonder machine for the semiconductor will be described. This is a final research results carried out for two years from June, 1986 to July, 1988. The mechanical system consists of three subsystems such as bonding head module, wafer feeding module, and lead frame feeding module. The overall control system consists of the following three subsystems each of which employs a 16 bit microprocessor MC 68000 : (i) supervisory control system, (ii) visual recognition / inspection system and (iii) the display system. Specifically, the supervisory control system supervises the whole sequence of die bonder machine, performs a self-diagnostics while it controls the bonding head module according to the prespecified bonding cycle. The vision system recognizes the die to inspect the die quality and deviation / orientation of a die with respect to a reference position, while it controls the wafer feeding module. Finally, the display system performs a character display, image display ans various error messages to communicate with operator. Lead frame feeding module is controlled by this subsystem. It is reported that the proposed control system were applied to an engineering sample and tested in real-time, and the results are sucessful as an engineering sample phase.

• 센서학회지
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• 제31권6호
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• pp.361-365
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• 2022

Advanced packaging demands are driven by the need for dense integration systems. Consequently, stacked packaging technology has been proposed instead of reducing the ultra-fine patterns to secure economic feasibility. This study proposed an effective packaging process technology for semiconductor devices using a 9-inch dicing die attach film (DDAF), wherein the die attach and dicing films were combined. The process involved three steps: tape lamination, dicing, and bonding. Following the grinding of a silicon wafer, the tape lamination process was conducted, and the DDAF was arranged. Subsequently, a silicon wafer attached to the DDAF was separated into dies employing a blade dicing process with a two-step cut. Thereafter, one separated die was bonded with the other die as a substrate at 130 ℃ for 2 s under a pressure of 2 kgf and the chip was hardened at 120 ℃ for 30 min under a pressure of 10 kPa to remove air bubbles within the DAF. Finally, a curing process was conducted at 175 ℃ for 2 h at atmospheric pressure. Upon completing the manufacturing processes, external inspections, cross-sectional analyses, and thermal stability evaluations were conducted to confirm the optimality of the proposed technology for application of the DDAF. In particular, the shear strength test was evaluated to obtain an average of 9,905 Pa from 17 samples. Consequently, a 3D integration packaging process using DDAF is expected to be utilized as an advanced packaging technology with high reliability.

• 열처리공학회지
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• 제26권4호
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• pp.178-184
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• 2013

The effects of thickness and surface grinding condition on the fracture strength of Si wafer with a thickness under $100{\mu}m$ were investigated. Fracture strength was measured by ball breaker test for about 330 dies (size: $4mm{\times}4mm$) per each wafer. For statistical analysis of the fracture strength, scale factor was determined from Weibull plot. Ball breaker fracture strength was observed to increase with decreasing thickness of silicon die. For the silicon dies of different surface conditions, ball breaker fracture strength was high in the order of polished, ground (#4800), and ground (#320 grit) specimen. Probabilistic fracture strength (i.e., scale factor) increased with decreasing surface roughness of silicon die.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2001년도 춘계학술대회 논문집
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• pp.1121-1124
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• 2001

In this study, we verify th effects of pattern density on interlayer dielectric chemical mechanical polishing process based on the analysis of Preston's equation and confirm this analysis by several experiments. Appropriate modeling equation, transformed form Preston's equations used in glass polishing, will be suggested and described the effects of this modeling during pattern wafer ILD CMP. Results indicate that the modeling is well agreed to middle density structure of the die in pattern wafer, but has some error in low and high density structure of the die. Actually, the die used in Fab, was designed to have a appropriate density, therefore this modeling will be suitable for estimating the results of ILD CMP.

• 한국반도체및디스플레이장비학회:학술대회논문집
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• 한국반도체및디스플레이장비학회 2006년도 춘계학술대회
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• pp.251-254
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• 2006

In this paper, cutting qualifies and fracture strength of silicon dies by laser dicing are investigated. Laser micromachining is the non-contact process using thermal ablation and evaporation mechanisms. By these mechanisms, debris is generated and stick on the surface of wafer, which is the problem to apply laser dicing to semiconductor manufacture process. Unlike mechanical sawing using diamond blade, chipping on the surface and crack on the back side of wafer isn't made by laser dicing. Die strength by laser dicing is measured via the three-point bending test and is compared with the die strength by mechanical sawing. As a results, die strength by the laser dicing shows a decrease of 50% in compared with die strength by the mechanical sawing.

• 한국재료학회지
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• 제17권7호
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• pp.347-351
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• 2007

Vertical interconnect technology called 3D stacking has been a major focus of the next generation of IC industries. 3D stacked devices in the vertical dimension give several important advantages over conventional two-dimensional scaling. The most eminent advantage is its performance improvement. Vertical device stacking enhances a performance such as inter-die bandwidth improvements, RC delay mitigation and geometrical routing and placement advantages. At present memory stacking options are of great interest to many industries and research institutes. However, these options are more focused on a form factor reduction rather than the high performance improvements. In order to improve a stacked device performance significantly vertical interconnect technology with wafer level stacking needs to be much more progressed with reduction in inter-wafer pitch and increases in the number of stacked layers. Even though 3D wafer level stacking technology offers many opportunities both in the short term and long term, the full performance benefits of 3D wafer level stacking require technological developments beyond simply the wafer stacking technology itself.

• 한국시뮬레이션학회논문지
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• 제12권3호
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• pp.13-20
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• 2003

Semiconductor Manufacturing has emerged as one of the most important world industries. Even with the highly automated and precisely monitored facilities used to process the complex manufacturing steps in a near particle free environment, processing variations in wafer fabrication still exist. The causes of these variations may arise from equipment malfunctions, delicate and difficult processing steps, or human mistakes. In this paper, we could specify the cause stage and the cause equipment and take countermeasures at a speed by the conventional method, without depending on the experience and skills of the engineer

• 반도체디스플레이기술학회지
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• 제5권1호
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• pp.5-11
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• 2006

One of the most important is to insure that a new circuit design is qualified far release before it is scheduled for manufacturing, test, assembly and delivery. Due to various causes, there happens to be a low yield in the wafer process. Wafer test is a critical process in analyzing the chip characteristics in the EDS(electric die sorting) using analytic tools -wafer map, wafer summary and datalog. In this paper, we propose new analytic map algorithms for DDI chip test data. Using the proposed analytic map algorithms, we expect to improve the yield, quality and analysis time.

• 마이크로전자및패키징학회지
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• 제18권1호
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• pp.15-21
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• 2011

전자기기의 고집적화를 위해 실리콘 웨이퍼의 두께가 점점 얇아지고 있으며 이로 인해 제조공정 중 균열이나 파손이 발생할 가능성이 높아지고 있다. 본 연구에서는 300 ${\mu}m$~100 ${\mu}m$ 두께의 반도체용 단결정 실리콘 웨이퍼의 파단 강도 및 파괴특성을 평가하였다. 기계적 연마를 통해 두께 (300, 200, 180, 160, 150, 100 ${\mu}m$)가 다른 실리콘 웨이퍼를 준비하였다. 하나의 웨이퍼에서 40개의 실리콘 다이(크기 : 62.5 mm${\times}$4 mm)를 얻어 4점 굽힘시험을 통해 평균 강도값을 구하였다. 강도분포의 통계적 해석을 위해 와이블 선도를 이용하여 형상인자(와이블 계수)와 크기인자(확률적 파괴강도)를 얻었다. 취성 실리콘 다이의 시편 크기(두께)효과와 파단 확률이 고려된 통계적 파단강도 값을 실리콘 다이 두께의 함수로 얻었다. 관찰된 파괴양상을 측정된 파단강도와 관련하여 고찰하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 춘계학술대회 논문집 반도체 재료 센서 박막재료 전자세라믹스
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• pp.129-132
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• 2004

This paper describes the design, fabrication and characteristics of a piezoelectric valve using MCA(Multilayer ceramic actuator). The MCA valve, which has the buckling effect, consists of three separate structures; MCA, a valve actuator die and an a seat die. The design of the actuator die was done by FEM modeling and displacement measurement, respectively. The valve seat die with 6 trenches was made, and the actuator die, which is driven to MCA under optimized conditions, was also fabricated. After Si-wafer direct bonding between the seat die and the actuator die, MCA was also anodic bonded to the seat/actuator die structure. PDMS sealing pad was fabricated to minimize a leak-rate. It was also bonded to seat die and SUS package. The MCA valve shows a flow rate of 9.13 sccm at a supplied voltage of 100 V with a 50 % duty cycle, maximum non-linearity was 2.24 % FS and leak rate was $3.03{\times}10^{-8}\;pa{\cdot}m^3/cm^2$. Therefore, the fabricated MCA valve is suitable for a variety of flow control equipment, a medical bio-system, automobile and air transportation industry.