• 제목/요약/키워드: Wafer Cleaning

검색결과 172건 처리시간 0.03초

반도체 습식 세정 공정 중 상온의 초순수와 염기성 수용액 내에서 오존의 용해도 최적화 (The Optimization of Ozone Solubility and Half Life Time in Ultra Pure Water and Alkaline Solution on Semiconductor Wet Cleaning Process)

  • 이상호;이승호;김규채;권태영;박진구;배소익;이건호;김인정
    • 반도체디스플레이기술학회지
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    • 제4권4호
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    • pp.19-26
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    • 2005
  • The process optimization of ozone concentration and half life time was investigated in ultra pure water and alkaline solutions for the wet cleaning of silicon wafer surface at room temperature. In the ultra pure water,. the maximum concentration (35 ppm) of ozone was measured at oxygen flow rate of 3 liters/min and ozone generator power over 60%. The half life time of ozone increased at lower power of ozone generator. Additive gases such as $N_2$ and $CO_2$ were added to increase the concentration and half life time of ozone. Although the maximum ozone concentration was higher with the addition of $N_2$ gas, a longer half life time was observed with the addition of $CO_2$. When $NH_4OH$ of 0.05 or 0.10 vol% was added in DI water, the pH of the solution was around 10. The addition of ozone resulted in the half life time less than 1 min. In order to maintain high pH and ozone concentration, ozone was continuously supplied in 0.05 vol% ammonia solutions. 3 ppm of ozone was dissolved in ammonia solutions. The static contact angle of silicon wafer surface became hydrophilic. The particle removal was possible alkaline ozone solutions. The organic contamination can be removed by ozonated ultra pure water and then alkaline solution containing ozone can remove the particles on silicon surface at room temperature.

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Effects of DC Biases and Post-CMP Cleaning Solution Concentrations on the Cu Film Corrosion

  • Lee, Yong-K.;Lee, Kang-Soo
    • Corrosion Science and Technology
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    • 제9권6호
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    • pp.276-280
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    • 2010
  • Copper(Cu) as an interconnecting metal layer can replace aluminum (Al) in IC fabrication since Cu has low electrical resistivity, showing high immunity to electromigration compared to Al. However, it is very difficult for copper to be patterned by the dry etching processes. The chemical mechanical polishing (CMP) process has been introduced and widely used as the mainstream patterning technique for Cu in the fabrication of deep submicron integrated circuits in light of its capability to reduce surface roughness. But this process leaves a large amount of residues on the wafer surface, which must be removed by the post-CMP cleaning processes. Copper corrosion is one of the critical issues for the copper metallization process. Thus, in order to understand the copper corrosion problems in post-CMP cleaning solutions and study the effects of DC biases and post-CMP cleaning solution concentrations on the Cu film, a constant voltage was supplied at various concentrations, and then the output currents were measured and recorded with time. Most of the cases, the current was steadily decreased (i.e. resistance was increased by the oxidation). In the lowest concentration case only, the current was steadily increased with the scarce fluctuations. The higher the constant supplied DC voltage values, the higher the initial output current and the saturated current values. However the time to be taken for it to be saturated was almost the same for all the DC supplied voltage values. It was indicated that the oxide formation was not dependent on the supplied voltage values and 1 V was more than enough to form the oxide. With applied voltages lower than 3 V combined with any concentration, the perforation through the oxide film rarely took place due to the insufficient driving force (voltage) and the copper oxidation ceased. However, with the voltage higher than 3 V, the copper ions were started to diffuse out through the oxide film and thus made pores to be formed on the oxide surface, causing the current to increase and a part of the exposed copper film inside the pores gets back to be oxidized and the rest of it was remained without any further oxidation, causing the current back to decrease a little bit. With increasing the applied DC bias value, the shorter time to be taken for copper ions to be diffused out through the copper oxide film. From the discussions above, it could be concluded that the oxide film was formed and grown by the copper ion diffusion first and then the reaction with any oxidant in the post-CMP cleaning solution.

Optimization of Selective Epitaxial Growth of Silicon in LPCVD

  • Cheong, Woo-Seok
    • ETRI Journal
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    • 제25권6호
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    • pp.503-509
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    • 2003
  • Selective epitaxial growth (SEG) of silicon has attracted considerable attention for its good electrical properties and advantages in building microstructures in high-density devices. However, SEG problems, such as an unclear process window, selectivity loss, and nonuniformity have often made application difficult. In our study, we derived processing diagrams for SEG from thermodynamics on gas-phase reactions so that we could predict the SEG process zone for low pressure chemical vapor deposition. In addition, with the help of both the concept of the effective supersaturation ratio and three kinds of E-beam patterns, we evaluated and controlled selectivity loss and non-uniformity in SEG, which is affected by the loading effect. To optimize the SEG process, we propose two practical methods: One deals with cleaning the wafer, and the other involves inserting dummy active patterns into the wide insulator to prevent the silicon from nucleating.

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CMP 공정후 세정공정 여부에 따른 $Pb(Zr,Ti)O_3$ 박막 캐패시터의 피로 특성 (Fatigue Properties of $Pb(Zr,Ti)O_3$ Thin Film Capacitor by Cleaning Process in Post-CMP)

  • 전영길;김남훈;이우선
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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    • pp.139-140
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    • 2006
  • PZT박막은 비휘발성 재료로 유전율이 높고 항전력이 작으면서 잔류 분극랑이 크기 때문에 적합한 특성을 가지고 FeRAM에 매력적인 물질이다. CMP(chemical mechanical polishing)는 기존의 회생막의 전면 식각 공정과는 달리 특정 부위의 제거 속도를 조절함으로써 평탄화 하는 기술로 wafer 전면을 회전하는 탄성 패드 사이에 액상의 Slurry를 투입하여 연마하는 기술이다. 본 논문에서는 CMP 공정으로 제조한 PZT박막 캐패시터에서 CMP 후처리공정(세척)의 유무 및 종류에 따라 피로특성에 대하여 연구하였다, PZT 박막의 캐패시터의 피로 특성을 연구한 결과 CMP 후처리공정 SC-l용액을 사용하여 세정공정을 하였을때 가장 향상된 PZT 캐패시터의 피로특성이 나타났다.

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반도체/LCD PR 제거용 EC의 재이용 기술에 관한 연구 (A Study on Recycling Technology of EC for Semiconductor and LCD PR Stripping Process)

  • 문세호;채상훈
    • 대한전자공학회논문지SD
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    • 제46권10호
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    • pp.25-30
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    • 2009
  • 오존을 이용하여 PR 박리에 사용된 에틸렌 카보네이트계 박리 세정제를 재이용할 수 있는 기술에 대하여 연구함으로써 향후 고성능-저가격의 반도체, LCD 제조에서의 PR 박리 및 세정 공정에 적용할 수 있는 핵심 공정기술을 확보하였다. 이 기술을 적용하면 반도체 웨이퍼 및 LCD 평판의 PR 박리 세정을 보다 빠르고 저렴한 비용으로 수행할 수 있으므로 반도체 및 LCD 제작공정의 생산성을 향상시킬 수 있다.

딤플 패턴이 있는 실리콘 표면의 마찰특성 (Frictional Characteristics of Silicon Surface with Micro-dimple Pattern)

  • 유신성;허윤영;김대은
    • 한국정밀공학회지
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    • 제31권5호
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    • pp.451-457
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    • 2014
  • Surface roughness of mechanical components is an important factor which affects the tribological phenomena. Various surface patterns have been applied to surfaces to improve the tribological characteristics of mechanical components. In this work, the friction reduction effect of micropatterns on silicon was investigated. For this purpose, micro-dimple patterns were fabricated on silicon wafer by DRIE process. In the friction experiments silicone oil was used as lubricant. Also, the lubricant was cleaned to simulate a lubricant depleted condition. In depleted lubricated condition, friction coefficient of micro-pattern specimens was lower than specimens without micro-patterns. It was found that friction reduction effect of micro-pattern could be successfully maintained even after cleaning the lubricant on the surface.

A Cooled Deformable Bimorph Mirror for a High Power Laser

  • Lee Jun-Ho;Lee Young-Cheol;Kang Eung-Cheol
    • Journal of the Optical Society of Korea
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    • 제10권2호
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    • pp.57-62
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    • 2006
  • Adaptive optics (AO) has been applied in various fields including astronomy, ophthalmology and high power laser systems. An adaptive optics system for a high power laser is not significantly different from other AO systems in the point of configuration except that high energy absorbed by the deformable mirror distorts the deformable mirror surface and so degrades system performance. Currently we are researching a bimorph deformable mirror for beam cleaning of a high power class laser. The bimorph mirror was considered to have 99% reflective coating and 1% absorption. So this paper first presents the temperature profiles and corresponding thermal distortions of the bimorph mirror faceplate when the mirror is under a high power lasing for 10 seconds. The analysis was accomplished by the use of finite difference and finite element computer programs to generate the element arrays, calculate the temperature profiles, and determine the structural deformations. Then this paper proposes an 'embedded wafer' type water-cooling system with derived cooling parameters.

평판 디스플레이 세정을 위한 상압 플라즈마 에싱효과에 관한 연구 (A Study on Ashing Effects of Atmospheric Plasma for the Cleaning of Flat Panel Display)

  • 허용정;이건영
    • 반도체디스플레이기술학회지
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    • 제7권2호
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    • pp.35-38
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    • 2008
  • This study shows the improvement of PR-Ashing rates in semi-conductor process using Atmospheric Plasma. Taguchi method is used to improve Ashing rates of photo-resist that is spread on the surface of a wafer. Improvement of Ashing rates is acquired through the decision of the effective factors and suitable combination of the factors. The results show the contribution rate of each factor and the effectiveness of Plasma for PR-Ashing process in this system.

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Wet Station 장비를 제어하기 위한 모니터링 시스템의 설계 (Design of a Monitoring System for Controlling the Wet Station Equipment)

  • 임성락;한광록;최용엽
    • 한국정보처리학회논문지
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    • 제6권5호
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    • pp.1385-1392
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    • 1999
  • 본 논문에서는 웨이퍼를 세정하는데 사용되는 Wet Station 장비의 상태를 감지하고, 이를 간접적으로 제어하기 위한 모니터링 시스템의 설계에 관하여 기술한다. 대부분의 기존 모니터링 시스템은 하드웨어 및 소프트웨어에 의존되어 있다. 제시한 모니터링 시스템의 기본 설계 목표는 사용자의 편의성과 시스템의 이식성을 제공하는 것이다. 이러한 요구조건을 만족시키기 위하여, 본 논문에서는 IBM PC 호환 기종의 윈도우즈 NT 환경에서 GUL 기능과, TCP/IP 통신 프로토콜을 기본으로 한 EtherNet 보드를 이용하여 시스템을 설계하였다.

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Etch Rate of Oxide Grown on Silicon Implanted with Different Ion Implantation Conditions prior to Oxidation

  • Joung, Yang-Hee;Kang, Seong-Jun
    • Journal of information and communication convergence engineering
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    • 제1권2호
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    • pp.67-69
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    • 2003
  • The experimental studies for the etch properties of the oxide grown on silicon substrate, which is in diluted hydrogen fluoride (HF) solution, are presented. Using different ion implantation dosages, dopants and energies, silicon substrate was implanted. The wet etching in diluted HF solution is used as a mean of wafer cleaning at various steps of VLSI processing. It is shown that the wet etch rate of oxide grown on various implanted silicon substrates is a strong function of ion implantation dopants, dosages and energies. This phenomenon has never been reported before. This paper shows that the difference of wet etch rate of oxide by ion implantation conditions is attributed to the kinds and volumes of dopants which was diffused out into $SiO_2$ from implanted silicon during thermal oxidation.