• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2011년도 제41회 하계 정기 학술대회 초록집
• /
• pp.305-305
• /
• 2011

Type-II 반도체 나노 구조는 그것의 band alignment 특성으로 인해 광학 소자에 다양한 응용성을 가진다. 특히, 대표적인 Type-II 반도체 나노 구조인 InSb/InAs 양자점의 경우, 약 3~5 ${\mu}m$의 mid-infrared 영역의 spectral range를 가지므로, 장파장을 요하는 소자에 유용하게 적용될 수 있다. 또한, Type-II 반도체 나노 구조의 밴드 구조를 staggered gap 혹은 broken gap 구조로 조절함으로써 infrared 영역 광소자의 전자 구조를 유용하게 바꾸어 적용할 수 있다. 최근, GaSb wafer 위에 InSb/InAsSb 양자점을 이용하여 cutoff wavelength를 6 ${\mu}m$까지 연장한 IR photodetector의 연구도 보고되고 있다. 하지만, GaSb wafer의 경우 그것의 비용 문제로 인해 산업적 적용이 쉽지 않다는 문제가 있다. 이러한 문제를 해결하기 위해 GaAs wafer와 같은 비용 효율이 높은 wafer를 사용한 연구가 필요할 것이다. 본 연구에서는 Molecular Beam Epitaxy(MBE)를 이용하여 undoped InAs wafer 와 semi-insulating GaAs wafer 상에 InSb 양자 구조를 형성한 결과를 보고한다. InSb 양자 구조는 20층 이상의 다층으로 형성되었고, 두 가지 경우 모두 400${\AA}$ spacer를 사용하였다. 단, InAs wafer 위에 형성한 InSb 양자 구조의 경우 InAs spacer를, GaAs wafer 위에 형성한 양자 구조의 경우 InAsSb spacer를 사용하였다. GaAs wafer 위에 양자 구조를 형성한 경우, InSb 물질과의 큰 lattice mismatch 차이 완화 뿐 아니라, type-II 밴드 구조 형성을 위해 1 ${\mu}m$ AlSb 층과 1 ${\mu}m$ InAsSb 층을 GaAs wafer 위에 미리 형성해 주었다. 양자 구조 형성 방법도 두 종류 wafer 상에서 다르게 적용되었다. InAs wafer 상에는 주로 일반적인 S-K 형성 방식이 적용된 것에 반해, GaAs wafer 상에는 migration enhanced 방식에 의해 양자 구조가 형성되었다. 이처럼 각 웨이퍼에 대해 다른 성장 방식이 적용된 이유는 InAsSb matrix와 InSb 물질 간의 lattice mismatch 차이가 6%를 넘지 못하여 InAs matrix에 비해 원하는 양자 구조 형성이 쉽지 않기 때문이다. 두 가지 경우에 대해 AFM과 TEM 측정으로 그 구조적 특성이 관찰되었다. 또한 infrared 영역의 소자 적용 가능성을 보기 위해 광학적 특성 측정이 요구된다.

• 한국재료학회지
• /
• 제8권10호
• /
• pp.890-897
• /
• 1998

n-InP(001)기판과 PECVD법으로 ${Si}_3N_4$(200nm)막이 성장된 InP 기판사이의 direct wafer bonding을 분석하였다. 두 기판을 접촉시켰을 때 이들 사이의 결합력에 크게 영향을 주는 표면 상태를 접촉각 측정과 AFM을 통해서 분석하였다. InP 기판은 $50{\%}$ 불산용액으로 에칭하였을 때 접촉각이 $5^{\circ}$, RMS roughness는 $1.54{\AA}$이었다. ${Si}_3N_4$는 암모니아수 용액으로 에칭하였을 때 RMS roughness가 $3.11{\AA}$이었다. Inp 기판과 ${Si}_3N_4$/InP를 각각 $50{\%}$ 불산 용액과 암모니아수 용액에 에칭한 후 접촉시켰을 때 상당한 크기의 초기 겹합력을 관찰할 수 있었다. 기계적으로 결합된 시편을 $580^{\circ}C$-$680^{\circ}C$, 1시간동안 수소 분위기와 질소분우기에서 열처리하였다. SAT(Scanning Acoustic Tomography)측정으로 두 기판 사이의 결합여부를 확인하였다. shear force로 측정한 InP 기판과 ${Si}_3N_4$/InP사이의 결합력은 ${Si}_3N_4$/InP 계면의 결합력만큼 증가되었다. TEM과 AES를 이용해서 di-rect water bonding 계면과 PECVD계면을 분석하였다.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2004년도 하계학술대회 논문집 C
• /
• pp.1820-1822
• /
• 2004

In this study, major research fields are classified as ozone generation system for dry cleaning wafer of etched silicon wafer, dry cleaning process of etched silicon wafer which includes SEM analysis and ESCA analysis. The following results are deduced from each experiment and analysis. The magnitudes of carbon and silicon were similar to the survey spectrum of silicon wafer which does not cleaning, but magnitude of oxygen was much bigger Because UV light activates oxygen molecules in the oxide film on the silicon wafer.

• 한국정밀공학회:학술대회논문집
• /
• 한국정밀공학회 1997년도 추계학술대회 논문집
• /
• pp.935-938
• /
• 1997

Recently, the minimum line width shows a tendency to decrease and the multi-level increase in semiconductor. Therefore, a planarization technique is needed and chemical mechanical polishing(CMP) is considered as one of the most suitable process. CMP accomplishes a high polishing performance and a global planarization of high quality. But there are several defects in CMP such as micro-scratches, abrasive contaminations, and non-uniformity of polished wafer edges. Wet etching include of Spin-etching can improve he defects of CMP. It uses abrasive-free chemical solution instead of slurry. On this study, ILD(INterlayer-Dielectric) was removed by CMP and wet-etching methods in order to investigate the superiority of wet etching mechanism. In the thin film wafer, the results were evaluated at a viewpoint of material removal rate(MRR) and within wafer non-uniformity(WIWNU). And pattern step height was also compared for planarization characteristics of the patterned wafer.

• 한국광학회:학술대회논문집
• /
• 한국광학회 2000년도 제11회 정기총회 및 00년 동계학술발표회 논문집
• /
• pp.224-225
• /
• 2000

Transparent and hard materials such as sapphire are used for many industrial applications as optical windows, hard materials on mechanical contact against abrasion, and substrate materials for opto-electronic semiconductor devices such as blue LED and blue LD etc. The materials should be cut along the proper shapes possible to be used for each application. In case of blue LED, the blue LED wafer should be cut to thousands of blue LED pieces at the final stage of the manufacturing process. The process of cutting the wafer is usually divided into two steps. The wafer is scribed along the proper shapes in the first step. It is inserted between transparent flexible sheets for easy handling. And then, it is broken and split in the next step. Harder materials such as diamonds are usually used to scribe the wafer, while it has a problem of low depth of scribing and abrasion of the harder material itself. The low depth of scribing can induce failure in breaking the wafer along the scribed line. It was also known that the expensive diamond tip should be replaced frequently for the abrasion. (omitted)

• 한국가시화정보학회지
• /
• 제13권3호
• /
• pp.24-28
• /
• 2015

The temperature of the wafer batch in the furnace was calculated and its visualized temperature field was analyzed. The main heat transfer mechanisms from the heater wall to the wafers were radiation and conduction, and the finite difference method was used to analyze the complex heat transfer including those two mechanisms. The visualized temperature field shows that the direction of the heat flux in the wafer batch varies during the heating process, and the heat in the wafer batch diffuses faster by conduction within the wafer than by radiation between the wafers, in the condition of the constant temperature at the heater wall and cap.

• 한국정밀공학회지
• /
• 제17권5호
• /
• pp.70-75
• /
• 2000

After the patterning and probe process of wafer have been achieved, the dicing process is necessary to separate chips from a wafer. The dicing process cuts a wafer to lengthwise and crosswise direction to make many chips by using narrow circular rotating diamond blade. But inferior goods are made under the influence of complex dicing environment such as blade, wafer, cutting water and cutting conditions. This paper describes a monitoring algorithm using feature extraction in order to find out an instant of vibration signal change when bad dicing appears. The algorithm is composed of two steps: feature extraction and decision. In the feature extraction, two features processed from vibration signal which is acquired by accelerometer attached on blade head are proposed. In the decision. a threshold method is adopted to classify the dicing process into normal and abnormal dicing. Experiment have been performed for GaAs semiconductor wafer. Based upon observation of the experimental results, the proposed scheme shown a good accuracy of classification performance by which the inferior goods decreased from 35.2% to 12.8%.

• 유공압시스템학회논문집
• /
• 제8권3호
• /
• pp.14-20
• /
• 2011

This study aims at aligning multiple wafers to reduce wafer handling time in wafer processes. We designed a multilevel structure for a prealigner which can handle multiple wafer simultaneously in a system. The system consists of gripping parts, kinematic parts, vacuum chucks, pneumatic units, hall sensors and a DSP controller. Aligning procedure has two steps: mechanical gripping and notch finding. In the first step, a wafer is aligned in XY directions using 4-point mechanical contact. The rotational error can be found by detecting a signal in a notch using hall sensors. A dual prealigner was designed for 300mm wafers and constructed for a performance test. The accuracy was monitored by checking the movement of a notch in a machine vision. The result shows that the dual prealigner has enough performance as commercial products.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 1999년도 춘계학술대회 논문집
• /
• pp.211-213
• /
• 1999

In this paper, we documented the controlling oxide removal amount on the pattern wafer using removal rate and removal thickness of blanket wafer. There was the strong correlation relationship for both(correlation factor:0.7109). So, we could confirm the repeatability as applying for STI CMP process from the obtained linear formular. As the result of repeatability test, the difference of calculated polishing time and actual polishing time was 3.48 seconds based on total 50 lots. If this time is converted into the thickness, it is from 104$\AA$ to 167$\AA$. It is possible to be ignored because it is under the process margin.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2000년도 하계학술대회 논문집 C
• /
• pp.1510-1512
• /
• 2000

Due to the shrinking of the chip size and increasing of the complexity in the modern electronic devices. the defect of wafer are so important to decide the yield in the device process. The engineers has studied the wafer defects and the characteristics. They published lots of the experimental methods. I did an experiment the gettering effect of the defects due to the high temperature and the long time diffusion. Actually, As the thickness of the wafer backside polysilicon is thicker and the diffusion time is faster. the defects on the wafer are decreased. The polysilicon gram boundaries of the wafer backside played an important part as the defect gettering site.