• Journal of the Korea Concrete Institute
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• v.15 no.1
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• pp.110-116
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• 2003

Recently, as concrete structure becomes high rise and large scaled tendency, demands for high performance concrete such as high strength, high fluidity and high durability has been increased. Even though high performance concrete performs high strength, workability and durability, compared to with those of normal concrete, it is more brittle than normal concrete. Accordingly, this paper is intended to improve toughness and compressive strength through investigating the mechanical properties of the high performance concrete confined with metal lath, glass fiber and carbon fiber laterally in the case of 30% and 40% of W/B. According to the results, the compressive strength increases in order of metal lath, carbon fiber and glass fiber. Considering strain-stress curve with the kinds of material for lateral confinement, while brittleness failure occurs in plain concrete just after maximum load, it is improved in some degree in confined concrete due to increase of the strain by increase of toughness. Elastic modulus increases slightly in case of confined concrete, like the compressing strength.

• YAKHAK HOEJI
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• v.36 no.6
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• pp.538-547
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• 1992

Optimal synthetic condition of barium sulfate were investigated from the viewpoint of yield and bulkiness according to a randomized complete block design proposed by G.E.P. Box and K.B. Wilson. Barium chloride and magnesium sulfate were utilized as reactants in order to prepare barium sulfate in this study. It was found that optimum temperature range of reactant solutions was $60{\sim}100^{\circ}C$ and the optimum concentration range of the reactant solutions was $10{\sim}17.3%$ and $10{\sim}20%$ respectively, on the viewpoint of yield and bulkiness. The optimum mole ratio of $BaCI_2$ to $BaSO_4$ was in the range of $1.50{\sim}2.0$ and the optimum mole ratio of $BaCI_2$ to $BaSO_4$ was in the range of $1.50{\sim}2.0$ and the optimum reacting time range was $15{\sim}20$ minutes. The optimum drying temperature range was $110{\sim}130^{\circ}C$ from the viewpoint of yield, but it was $90{\sim}110^{\circ}C$ on the basis of bulkiness. Apparent viscosity of barium sulfate suspensions dispersed in various concentrations of Na. CMC was measured by using Brookfield synchrolectric viscometer model LVT, the relative equation, log ${\eta}_{sp}=A+B.{\phi}$ was examined and the equation was found to agree fairly well. 1 w/v% Na. CMC aqueous solution and 0.1 volume fraction of $BaSO_4$ powder were optimum in the preparation of $BaSO_4$ suspension showing highest viscosity at infinite shearing.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.14 no.1
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• pp.1-6
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• 2000

In this paper, organic dispersion type back light EL(Electroluminescent) devices were manufactured using Ethyl hydroxy ethyl cellulose as organic binder, ZnS:Cu as phosphor powder and $BaTiO_3$ as dielectrics by screen printing method, which are focused on as a new light source. The properties of the fabricated organic dispersion type back light EL devices were showed $1.98[mA/\m^2]$ of current density, 0.075[W] of power consumption, 7.1[nF] of capacitance at $25[^{\circ}C]$, 100[V], 400[Hz], respectively. Also brightness of the fabricated device was revealed $20~110[cd/\m^2]$ at 50~150[V] and the change of color was shoed bluish green of x=0.1711, y=0.3676 which are color coordinate by CIE.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.1
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• pp.31-38
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• 2011

With the increasing demand for high-speed transmission systems, adaptive equalizers have been widely used in receivers to overcome the limited bandwidth of channels. In order to reduce the cost for testing high-speed receiver chips, on-chip eye-opening monitoring (EOM) technique which measures the eye-opening of data waveform inside the chip can be employed. In this paper, a 10-Gb/s adaptive 2-tap look-ahead decision feedback equalizer (DFE) with EOM function is proposed. The proposed EOM circuit can be applied to look-ahead DFEs while existing EOM techniques cannot. The magnitudes of the post-cursors are measured by monitoring the eye of received signal, and coefficients of DFE are calculated using them by proposed adaptation algorithm. The circuit designed in 90nm CMOS technology and the algorithm are verified with post-layout simulation. The DFE core occupies $110{\times}95{\mu}m^2$ and consumes 11mW in 1.2V supply voltage.

• Microbiology and Biotechnology Letters
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• v.37 no.4
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• pp.350-354
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• 2009

A Gram-negative, alginate lyase-producing bacterium was isolated from the Haeundae Coast, Korea. The isolated strain N7151-6 produced alginate lyase. The optimal temperature and pH for growth were found to be $30^{\circ}C$ and pH 8.0, respectively. This strain can be grown at the NaCl concentration of 0-7% (w/v). Analysis of 16S rDNA sequence and physiological profiling indicated that the strain N7151-6 belonged to Pseudomonas sp. The enzyme alginate lyase produced by Pseudomonas sp. N7151-6 was partially purified by ultrafiltration (MWCO= 30 kDa). The optimum pH and temperature for the activity of the purified enzyme were found to be 7.0 and $30^{\circ}C$, respectively. The enzyme was stable at the pH range of 5.0-9.0 and temperature range of $23-30^{\circ}C$. The total activity of alginate lyase produced was reached about 110 unit/L.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.3
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• pp.585-593
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• 2017

In this paper, we propose a deblocking filter hardware architecture for low-power HEVC (High-Efficiency Video Coding) in-loop for mobile systems. HEVC performs image compression on a block-by-block basis, resulting in blockage of the image due to quantization error. The deblocking filter is used to remove the blocking phenomenon in the image. Currently, UHD video service is supported in various mobile systems, but power consumption is high. The proposed low-power deblocking filter hardware structure minimizes the power consumption by blocking the clock to the internal module when the filter is not applied. It also has four parallel filter structures for high throughput at low operating frequencies and each filter is implemented in a four-stage pipeline. The proposed deblocking filter hardware structure is designed with Verilog HDL and synthesized using TSMC 65nm CMOS standard cell library, resulting in about 52.13K gates. In addition, real-time processing of 8K@84fps video is possible at 110MHz operating frequency, and operation power is 6.7mW.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.1
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• pp.159-165
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• 2018

In this paper, a low-loss wideband waveguide transducer is proposed for millimeter-wave communication and radar applications. A conventional E-plane probe transducer is generally designed using thin and flexible substrate at millimeter-wave frequencies, considering the very small waveguide size. However, it results in serious performance degradation caused by the bending of the substrate. In order to alleviate this problem and provide a reliable performance, we propose an extended E-plane probe transducer where the probe substrate is extended to and fix ed in the slit area formed in the waveguide wall. It is fabricated using $127{\mu}m$-thick substrate with dielectric constant of 2.2. The measurement in the back-to-hack configuration shows the excellent insertion loss of 1.35 dB (${\pm}0.35dB$) including the loss of 3 cm-long thru waveguide and return loss better than 13.8 dB over entire W-band (75-110 GHz). Therefore, it can be effectively applied for millimeter-wave high-speed communications and high-sensitivity radars.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.3
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• pp.1-7
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• 2012

A 9b MS/s CMOS cyclic folding A/D converter (ADC) for intelligent battery sensor and battery management systems is proposed. The proposed ADC structure is based on a cyclic architecture to reduce chip area and power consumption. To obtain a high speed ADC performance, further, we use a folding-interpolating structure. The prototype ADC implemented with a 0.35um 2P4M n-well CMOS process shows a measured INL and DNL of maximum 1.5LSB and 1.0LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 48dB and 60dB, respectively, and the power consumption is about 110mW at 2MS/s and 3.3V. The occupied active die area is $10mm^2$.

• Transactions of the Korean Society of Mechanical Engineers
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• v.10 no.1
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• pp.110-120
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• 1986

45.deg. corss jet flow, at the mixing of two jet flows, was experimentally studied. For this study, only the statistical turbulent characteristics and high order moments will be analysed by on-line computer system (hot-wire anemometer system, dynamic analyser and computer system, plotting and printing system). Since mean velocity distributions, intensities of turbulence, Reynolds stresses, correlation coefficients, and other general results were already studied and presented. One dimensional probability density distributions of u', v', and w' were analysed comparing with Gaussian curve, which showed skew and flat tendency according to the Y and Z directions. For the analysis of the joint flow of turublent components, the joint probability density distributions were examined. The fagures were drawn so as to be read joint probabilities, joint probability densities, fluctuating velocities u', v', and w'. For further detailed examination of the variations of skewness and flatness phenomena, iso-joint probability density contours obtained from the profiles of the joint probability density distributions were studied. According to the displacement of positions from the center of the mixing flow and the directions, the flatness and skewness factors were increased.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.18-27
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• 2010

In this paper, a 1.2V 7-bit 1GSPS A/D converter with offset self-calibration is proposed. The proposed A/D converter structure is based on the folding-interpolation whose folding rate is 2, interpolation rate is 8. Further, for the purpose of improving the chip performance, an offset self-calibration circuit is used. The offset self-calibration circuit reduce the variation of the offset-voltage，due to process mismatch, parasitic resistor, and parasitic capacitance. The chip has been fabricated with a 1.2V 65nm 1-poly 6-metal CMOS technology. The effective chip area is $0.87mm^2$ and the power dissipates about 110mW at 1.2V power supply. The measured SNDR is about 39.1dB when the input frequency is 250MHz at 800MHz sampling frequency. The measured SNDR is 3dB higher than the same circuit without any calibration.