• Journal of Power Electronics
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• 제17권1호
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• pp.67-75
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• 2017

Due to the excessive zero-sequence voltage in dual three-level inverter fed open-end winding induction motor systems, zero-sequence circumfluence which is harmful to switching devices and insulation is then formed when operating in a single DC voltage source supplying mode. Traditionally, it is the mean value instead of instantaneous value of the zero-sequence voltage that is eliminated, through adjusting the durations of the operating vectors. A new strategy is proposed for zero-sequence voltage elimination, which utilizes unified voltage modulation and a decoupled SVPWM strategy to achieve two same-sized equivalent vectors for an angle of $120^{\circ}$, generated by two inverters independently. Both simulation and experimental results have verified its efficiency in the instantaneous value elimination of zero-sequence voltage.

• Journal of Power Electronics
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• 제11권4호
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• pp.576-582
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• 2011

This paper presents a novel control strategy for selective compensation of power quality (PQ) problems, depending upon the limited rating of voltage source inverters (VSIs), through a unified power quality conditioner (UPQC) in a three-phase four-wire distribution system. The UPQC is realized by the integration of series and shunt active power filters (APFs) sharing a common dc bus capacitor. The shunt APF is realized using a three-phase, four-leg voltage source inverter (VSI), while a three-leg VSI is employed for the series APF of the three-phase four-wire UPQC. The proposed control scheme for the shunt APF, decomposes the load current into harmonic components generated by consumer and distorted utility. In addition to this, the positive and negative sequence fundamental frequency active components, the reactive components and harmonic components of load currents are decomposed in synchronous reference frame (SRF). The control scheme of the shunt APF performs with priority based schemes, which respects the limited rating of the VSI. For voltage harmonic mitigation, a control scheme based on SRF theory is employed for the series APF of the UPQC. The performance of the proposed control scheme of the UPQC is validated through simulations using MATLAB software with its Simulink and Power System Block set toolboxes.

• Journal of Power Electronics
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• 제16권6호
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• pp.2272-2283
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• 2016

This paper proposes a power conditioning system (PCS) for distributed photovoltaic (PV) applications using an asymmetric cascaded multilevel inverter with a single PV source. One of the main disadvantages of the cascaded multilevel inverters in PV systems is the requirement of multiple isolated DC sources. Using multiple PV strings leads to a compromise in either the voltage balance of individual H-bridge cells or the maximum power point tracking (MPPT) operation due to localized variations in atmospheric conditions. The proposed PCS uses a single PV source with a flyback DC-DC converter to facilitate a reduction of the required DC sources and to maintain the voltage balance during MPPT operation. The flyback converter is used to provide input for low-voltage H-bridge cells which processes only 20% of the total power. This helps to minimize the losses occurring in the proposed PCS. Furthermore, transient analyses and controller design for the proposed PCS in both the stand-alone mode and the grid-connection mode are presented. The feasibility of the proposed PCS and its control scheme have been tested using a 1kW hardware prototype and the obtained results are presented.

• Journal of Power Electronics
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• 제8권2호
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• pp.171-180
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• 2008

One of the major problems in electric power quality is the harmonic contents. There are several methods of indicating the quantity of harmonic contents. The most widely used measure is the total harmonic distortion (THD). Various switching techniques have been used in static converters to reduce the output harmonic content. This paper presents and compares the two harmonic optimization techniques, known as optimal minimization of the total harmonic distortion (OMTHD) technique and optimized harmonic stepped-waveform (OHSW) technique used in multi-level inverters with unequal dc sources. Both techniques are very effective and efficient for improving the quality of the inverter output voltage. First, we describe briefly the cascaded H-bridge multi-level inverter structure. Then, we present the switching algorithm for the inverter based on OHSW and OMTHD techniques. Finally, the results obtained for the two techniques are analyzed and compared. The results verify the effectiveness of the both techniques in multi-level voltage-source inverter with non-equal dc sources, clarifying the advantages of each technique.

• 전력전자학회논문지
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• 제17권5호
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• pp.453-460
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• 2012

This paper proposes the method to design the parameters of an impedance network at three-phase QZSI(quasi Z-source inverter) by considering an equivalent series resistance (ESR) in the capacitor. The equations of both two capacitor voltages and two inductor currents are derived at three operating modes of the QZSI. The capacitor voltage ripples caused by the ESR in the capacitor at the transition state of operating modes are calculated. Based on the ripples of both the capacitor voltages and inductor currents, the optimal values of capacitor and inductor are designed. The simulation studies using PSIM and experimental results with DSP are carried out to verify the performance of design method.

• Journal of Power Electronics
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• 제14권2호
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• pp.292-301
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• 2014

This paper presents a new configuration for a three-phase multilevel voltage source inverter. The main bridge is built from a classical three-phase two-level inverter and three bidirectional switches. A variable DC-link employing two unequal DC voltage supplies and four switches is connected to the main circuit in such a way that the proposed inverter produces four levels in the output voltage waveform. In order to obtain the desired switching gate signals, the fundamental frequency staircase modulation technique is successfully implemented. Furthermore, the proposed structure is extended and compared with other types of multilevel inverter topologies. The comparison shows that the proposed inverter requires a smaller number of power components. For a given number of voltage steps N, the proposed inverter requires N/2 DC voltage supplies and N+12 switches connected with N+7 gate driver circuits, while diode clamped or flying capacitor inverters require N-1 DC voltage supplies and 6(N-1) switches connected with 6(N-1) gate driver circuits. A prototype of the introduced configuration has been manufactured and the obtained simulation and experimental results ensure the feasibility of the proposed topology and the validity of the implemented modulation technique.

• 전기전자학회논문지
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• 제27권3호
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• pp.319-326
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• 2023

본 논문에서는 단상 전압 소스 인버터 (VSIs)의 강인한 출력 전압 제어를 위한 디지털 제어기 구현과 총 고조파 왜곡(T.H.D.v) 분석을 포함한 시뮬레이션 및 실험 결과를 제시한다. 일반적으로 VSI는 내부 루프의 전류 제어기에 비례 적분(PI) 제어기를 사용하고 외부 루프의 전압 제어기에 비례 공진 (PR) 제어기가 사용된다. 그러나, 비선형 부하에서 여전히 3차, 5차 및 7차와 같은 고차 고조파 왜곡이 발생한다. 따라서 본 논문에서는 고조파 왜곡을 억제하기 위해 홀수 고조파 주파수에 대한 공진 제어기를 포함한 비례 다중 공진 (PMR) 제어기를 제안한다. VSI 플랜트용 컨트롤러의 주파수 응답을 분석하고 PMR 컨트롤러를 설계합니다. 시뮬레이션을 통해 PI와 PMR을 전압 제어기로 사용할 때 출력 전압의 총 고조파 왜곡 특성을 비교 검증합니다. 선형 및 비선형 하중 조건이 모두 고려되었습니다. 마지막으로 PMR 제어기를 3kW급 VSIs 프로토 타입에 적용하여 그 유효성을 입증하였다.

• 전력전자학회논문지
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• 제19권4호
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• pp.332-341
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• 2014

A cascaded H-bridge multi-level STATCOM(STATic synchronous COMpensator), which is composed of many cell inverters with independent dc-sources, generates inevitably dc-side voltage unbalance among phases when it compensates unbalanced load. It comes from the difference of flowing active power in each phase when this compensator makes negative-sequence current to eliminate the unbalance of source-side current. However, this unbalance can be controlled by injecting zero-sequence current which is decoupled with grid currents, so the compensator can work well during this balancing process. Both a feedback control algorithm, which produces zero-sequence current proportional to dc-side voltage unbalance within each phase, and a feedforward control algorithm, which makes zero-sequence current directly from the compensator's negative-sequence current, were proposed. The dc-side voltage of each phase can be controlled stably by these proposed algorithms in both steady-state and transient, so the compensator can have fast response to satisfy control performance under rapid changing load. These balancing controllers were implemented and verified via simulation and experiment.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2016년도 전력전자학술대회 논문집
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• pp.485-486
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• 2016

This paper proposes a new hybrid five-level voltage-source inverter topology, based on the conventional five-level active neutral-point-clamped topology (5L-ANPC), where the lower number of switching devices is required, resulting in saving the cost. The operating principle and control method of the proposed topology is described. The comparison of THD, power losses, loss distribution, and cost of components are evaluated among the proposed topology, the 5L-ANPC and 5L-DCI (diode-clamped inverters) topology.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2001년도 Proceedings ICPE 01 2001 International Conference on Power Electronics
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• pp.31-35
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• 2001

IGCTs have established themselves as the power semiconductor of choice at medium voltage levels within the last few years because of their low conduction and switching losses. The trade-off between these losses can be adjusted by various lifetime control techniques and the growing demand for these devices is driving the need for standard types to cover such applications as Static Circuit Breakers (low on-state) and Medium Voltage Drives (low switching losses). The additional demands of Traction (low operating temperatures) and Current Source Inverters (symmetric blocking) would normally result in conflicting demands on the semiconductor. This paper will outline how a range of power devices can meet these needs with a limited number of wafers and gate units. Some of the key differences between IGCTs and IGBTs will be explained and the outlook for device improvements will be discussed.