• 대한전기학회논문지:전력기술부문A
• /
• 제52권6호
• /
• pp.295-300
• /
• 2003

Voltage instability has been studied for some decade now. But, There is not generally accepted definition of voltage instability because of the complex phenomenon and the variety of ways in which it can manifest itself. Both IEEE and CIGRE have the respective definitions. The areas of voltage instability research are the analysis, simulation and countermeasure of voltage instability. It needs to model the components of the power system to simulate the voltage instability and voltage collapse. At the beginning, the static simulation was used. This method provides the voltage stability indices and it requires less CPU resource and gives much insight into the voltage and power problem. However, it is less accurate than the dynamic simulation peformed in the time domain simulation. So, when it appears difficult to secure the voltage stability margin in a static stability, it is necessary to perform the dynamic simulation. To perform time-domain simulation, we have to model the dynamic component of the power system like a generator and a load. The dynamic simulation provides the accurate result of the voltage instability. But, it is not able to provide the sensitivity information or the degree of stability and it is time consuming and it needs much CPU resource. In this Paper, we perform a dynamic simulation of voltage instability and voltage collapse using EMTP MODELS. The exponential load model is designed with MODEIS and this load model is connected with test power system. The result shows the process of voltage change in time domain when the voltage instability or voltage collapse occurs.

• 센서학회지
• /
• 제20권1호
• /
• pp.14-18
• /
• 2011

An analytical pinning-voltage model of a pinned photodiode has been proposed and derived. The pinning-voltage is calculated using doping profiles based on shallow- and exponential-junction approximations. Therefore, the derived pinning-voltage model is analytically expressed in terms of the process parameters of the implantation. Good agreement between the proposed model and simulated results has been obtained. Consequently, the proposed model can be used to predict the pinning-voltage and related performance of a pinned photodiode in a CMOS active pixel sensor.

• Journal of information and communication convergence engineering
• /
• 제8권1호
• /
• pp.107-111
• /
• 2010

This paper has presented the dependence of the threshold voltage on back gate bias and drain voltage for FinFET. The FinFET has three gates such as the front gate, side and back gate. Threshold voltage is defined as the front gate bias when drain current is 1 micro ampere as the onset of the turn-on condition. In this paper threshold voltage is investigated into the analytical potential model derived from three dimensional Poisson's equation with the variation of the back gate bias and drain voltage. The threshold voltage of a transistor is one of the key parameters in the design of CMOS circuits. The threshold voltage, which described the degree of short channel effects, has been extensively investigated. As known from the down scaling rules, the threshold voltage has been presented in the case that drain voltage is the 1.0V above, which is set as the maximum supply voltage, and the drain induced barrier lowing(DIBL), drain bias dependent threshold voltage, is obtained using this model.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
• /
• 제11B권4호
• /
• pp.164-168
• /
• 2001

In this paper voltage source FEA for hysteresis motor considering magnetic hysteresis characteristics is presented. The Preisach model is used as a hysteresis model. System matrix whose unknown variables are vector potentials and currents is formulated for voltage source. The stiffness matrix is maintained constant by using M-iteration method. Therefore the calculation time and efforts are reduced with Choleski direct method. Current waveform can be calculated for arbitrary voltage vaveform considering hysteresis effects.

• 한국정보기술응용학회:학술대회논문집
• /
• 한국정보기술응용학회 2005년도 6th 2005 International Conference on Computers, Communications and System
• /
• pp.99-102
• /
• 2005

In the paper, a proposed VCO based on bondwire inductances and nMOS varactors was implemented in a standard $0.25\;{\mu}m$ CMOS process. Using the new drain current model and a propagation delay time model equations, the operation speed of CMOS gate will predict the dependence on the load capacitance and the depth of oxide, threshold voltage, the supply voltage, the channel length. This paper describes the result of simulation which calculated a gate propagation delay time by using new drain current model and a propagation delay time model. At the result, When the reverse bias voltage on the substrate changes from 0 voltage to 3 voltage, the propagation delay time is appeared the delay from 0.8 nsec to 1 nsec. When the reverse voltage is biased on the substrate, for reducing the speed delay time, a supply voltage has to reduce. The $g_m$ value of MOSFET is calculated by using new drain current model.

• Journal of Power Electronics
• /
• 제16권6호
• /
• pp.2231-2242
• /
• 2016

A simplified model predictive control method is presented in this paper. This method is based on a future reference voltage vector for a three-phase four-leg voltage source inverter (VSI). Compared with the three-leg VSIs, the four-leg VSI increases the possible switching states from 8 to 16 owing to a fourth leg. Among the possible states, this should be considered in the model predictive control method for selecting an optimal state. The increased number of candidate switching states and the corresponding voltage vectors increase the calculation burden. The proposed technique can preselect 5 among the 16 possible voltage vectors produced by the three-phase four-leg voltage source inverters, based on the position of the future reference voltage vector. The discrete-time model of the future reference voltage vector is built to predict the future movement of the load currents, and its position is used to choose five preselected vectors at every sampling period. As a result, the proposed method can reduce calculation load by decreasing the candidate voltage vectors used in the cost function for the four-leg VSIs, while exhibiting the same performance as the conventional method. The effectiveness of the proposed method is demonstrated with simulation and experiment results.

• 한국조명전기설비학회:학술대회논문집
• /
• 한국조명전기설비학회 2004년도 춘계학술대회 논문집
• /
• pp.277-280
• /
• 2004

As electric shock accident take place frequently, electrical safety is extremely important to prevent them. This paper describes the characteristics of electric shock. In order to examine it, an experimental apparatus including a model of a human body is fabricated and the magnitude of the voltage held by the model is measured under several conditions as follows;(1) the model is not contacted to an electric pole and a step voltage does not exist. (2) the model is not contacted to an electric pole and a step voltage exists. (3) the model is contacted to an electric pole and a step voltage does not exist (4) the model is contacted to an electric pole and a step voltage exists. As a result of the experiment it is found that the voltage held by the model depends on the step voltage as well as the voltages applied to the electric pole.

• Journal of Power Electronics
• /
• 제19권6호
• /
• pp.1477-1485
• /
• 2019

This paper proposes an effective model predictive current control (MPCC) that involves using 10 virtual voltage vectors to reduce the current harmonics and common-mode voltage (CMV) for a two-level five-phase voltage source inverter (VSI). In the proposed scheme, 10 virtual voltage vectors are included to reduce the CMV and low-order current harmonics. These virtual voltage vectors are employed as the input control set for the MPCC. Among the 10 virtual voltage vectors, two are applied throughout the whole sampling period to reduce current ripples. The two selected virtual voltage vectors are based on location information of the reference voltage vector, and their duration times are calculated using a simple algorithm. This significantly reduces the computational burden. Simulation and experimental results are provided to verify the effectiveness of the proposed scheme.

• 한국전기전자재료학회논문지
• /
• 제36권2호
• /
• pp.129-135
• /
• 2023

An analytical threshold voltage model is presented to observe the change in threshold voltage shift ΔV_th of a junctionless double gate MOSFET using ferroelectric-metal-SiO₂ as a gate oxide film. The negative capacitance transistors using ferroelectric have the characteristics of increasing on-current and lowering off-current. The change in the threshold voltage of the transistor affects the power dissipation. Therefore, the change in the threshold voltage as a function of theferroelectric thickness is analyzed. The presented threshold voltage model is in a good agreement with the results of TCAD. As a results of our analysis using this analytical threshold voltage model, the change in the threshold voltage with respect to the change in the ferroelectric thickness showed that the threshold voltage increased with the increase of the absolute value of charges in the employed ferroelectric. This suggests that it is possible to obtain an optimum ferroelectric thickness at which the threshold voltage shift becomes 0 V by the voltage across the ferroelectric even when the channel length is reduced. It was also found that the ferroelectric thickness increased as the silicon thickness increased when the channel length was less than 30 nm, but the ferroelectric thickness decreased as the silicon thickness increased when the channel length was 30 nm or more in order to satisfy ΔV_th=0.

• 전기학회논문지
• /
• 제60권12호
• /
• pp.2281-2285
• /
• 2011

An algorithm for extracting SPICE MOS level 2 model parameters for the high voltage MOSFET DC model is proposed. The optimization method for analyzing the nonlinear data of the current-voltage curve using the Gauss-Newton algorithm is proposed and the pre-process step for calculating the threshold voltage and the mobility is proposed. The drain current obtained from the proposed method shows the maximum relative error of 5.6% compared with the drain current of 2-dimensional device simulation for the high voltage MOSFET.