• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.19-25
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• 2015

In this paper, a design method for a CPW-fed slot antenna for harmonic suppression is studied. The structure of the proposed slot antenna is a rectangular slot antenna appended with stepped impedance resonators (SIRs) at both ends of the slot symmetrically. Optimal design parameters are obtained by analyzing the effects of the length and width of the SIRs on the input reflection coefficient. The optimized harmonic-suppressed slot antenna operating at 2.45 GHz WLAN band is fabricated on an FR4 substrate with a dimension of 42 mm by 30 mm. The slot length of the proposed harmonic-suppressed slot antenna is reduced to 33.3% compared to that of a conventional rectangular slot antenna owing to the appended SIRs. Experiment results show that the antenna has a desired impedance characteristic with a frequency band of 2.39-2.49 GHz for a VSWR < 2, and a measured gain of 2.5 dBi at 2.45 GHz.

• Korean Journal of Materials Research
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• v.29 no.10
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• pp.586-591
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• 2019

This study describes the doping effect of $Yb_2O_3$ on microstructure, electrical and dielectric properties of $ZnO-V_2O_5-MnO_2-Nb_2O_5$ (ZVMN) ceramic semiconductors sintered at a temperature as low as $900^{\circ}C$. As the doping content of $Yb_2O_3$ increases, the ceramic density slightly increases from 5.50 to $5.54g/cm^3$; also, the average ZnO grain size is in the range of $5.3-5.6{\mu}m$. The switching voltage increases from 4,874 to 5,494 V/cm when the doping content of $Yb_2O_3$ is less than 0.1 mol%, whereas further doping decreases this value. The ZVMN ceramic semiconductors doped with 0.1 mol% $Yb_2O_3$ reveal an excellent nonohmic coefficient as high as 70. The donor density of ZnO gain increases in the range of $2.46-7.41{\times}10^{17}cm^{-3}$ with increasing doping content of $Yb_2O_3$ and the potential barrier height and surface state density at the grain boundaries exhibits a maximum value (1.25 eV) at 0.1 mol%. The dielectric constant (at 1 kHz) decreases from 592.7 to 501.4 until the doping content of $Yb_2O_3$ reaches 0.1 mol%, whereas further doping increases it. The value of $tan{\delta}$ increases from 0.209 to 0.268 with the doping content of $Yb_2O_3$.

• Journal of IKEEE
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• v.22 no.4
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• pp.953-958
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• 2018

In this study, a portable detection system was developed that can detect harmful gas and signals simultaneously in an enclosed space of industrial sites and underground facilities. The developed system is a sensor module for gas detection, a patch type 1 channel small ECG sensor, a module for three-axial acceleration detection sensor, and a system for statistics. In order to verify the performance of the system modules, the digital resolution, signal frequency, output voltage, and ultra-small modules were evaluated. As a result of the performance of the developed system, the digital resolution was 300 (rps) and the signal amplification gain was 500 dB or more, and the ECG module was manufactured with $50mm{\times}10mm{\times}10mm$ to increase patch utilization. It is believed that the product of this research will be valuable if it is used as an IoT-based management system for real-time monitoring of industrial workers.

• Journal of Advanced Navigation Technology
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• v.23 no.5
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• pp.430-436
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• 2019

It is needed to develop an antenna with features of subminiature, light weight and multi-band operation for the variaty services in maritime and industrial fields. The PCB pattern antenna is one of the appropreiate antennas solving these requirements. In this research, the design and fabrication of the PCB pattern antenna operating on the single band of 920 MHz are investigated. The final goal is that the development of the dual band PCB pattern antenna operating on 260 MHz and 920 MHz, which is based on the proposed antenna. It is evident that the performance in the frequencies of 902 MHz, 915 MHz and 928 MHz among of 920 MHz ISM band is better than that in other frequencies. It is also confirmed that the differences of the voltage standing wave ratio, return loss, gain and efficiency between three frequencies are less than 5%. It is expected that the development of communication link of 5-10 km is possible when the induced results are applied into the low power wide area (LPWA) network desinged by the rule of -30 dB sensitivity.

• Journal of Advanced Navigation Technology
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• v.26 no.1
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• pp.29-34
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• 2022

In this paper, the design of a triple dipole quasi-yagi antenna operating in the 2.45 GHz and 5 GHz wireless LAN frequency bands and the 3.5 GHz WiMAX frequency band was studied. The proposed quasi-Yagi antenna consists of three dipoles connected in series with a V-shaped ground plane. The longest half-bow-tie-shaped dipole resonates in the 2.45 GHz band, whereas the medium-length dipole resonates at 3.5 GHz. The shortest dipole resonates in the 5 GHz band. By adjusting the length and width of the dipoles and the spacings between the dipoles, a triple-band directional antenna operating in the 2.45 GHz, 3.5 GHz, and 5 GHz bands are designed, and fabricated on an FR4 substrate with a size of 45 mm × 55 mm. It was confirmed that the fabricated antenna operates in the designed triple bands of 2.32-2.57 GHz, 3.26-3.69 GHz, and 4.50-6.56 GHz for a voltage standing wave ratio less than 2. Gain is maintained above 3 dBi in the three bands.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.4
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• pp.67-72
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• 2022

This study presents the design of power amplifier (PA) in 60 nm GaN/Si HEMT technology. A customized transistor model enables the designing circuits operating at W-band. The all matching network of the PA was composed of equivalent transformer circuit to reduce matching loss. And then, equivalent transformer is several advantages without any additional inductive devices so that a wideband power characteristic can be achieved. The designed die area is 3900 ㎛ × 2300 ㎛. The designed results at center frequency achieved the small signal gain of 15.9 dB, the saturated output power (Psat) of 29.9 dBm, and the power added efficiency (PAE) of 24.2% at the supply voltage of 12 V.

• Journal of Advanced Navigation Technology
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• v.27 no.4
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• pp.463-468
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• 2023

In this paper, we proposed reconfigurable dual polarization patch array antenna that can select two polarizations(Vertical, RHCP) using defected ground structure and Pin diode. The proposed antenna was designed arranging a circular polarization patch antenna implemented with a square microstrip patch and two slots 3x3 at 25.8mm placed, a half-wavelength of 5.8 GHz. Conect the pin diode and the capacitor to the slot diagonally placed on the ground of each antennas, and select polarization using the open/short operating according to the application of DC voltage to the pin diode. As a result of the design, the gain of the antenna is 11.7 dBi at vertical polarization and 11.6 dBic at RHCP. The axial ratio is 20.3 dB at 1.8 dB vertical polarization at RHCP. Mutual Coupling is Maximum to -20.8 dB for vertical polarization and Maximum to -30.1 dB for RHCP.

• Journal of the Korea Society of Computer and Information
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• v.14 no.12
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• pp.17-24
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• 2009

More recently, the Green Computing have become a important issue in all fields of industry. The energy efficiency cannot be over-emphasized. Microprocessor companies such as Intel Corporation design processors with taking both energy efficiency and performance into account. Nevertheless, general computer users typically utilize the CPU overclocking to enhance the application performance. The overclocking is traditionally considered as an evil in terms of the power consumption. In this paper, we present effective CPU overclocking schemes, which raise CPU frequency while keeping current CPU supply voltage for energy reduction and performance improvement. The proposed scheme gain both energy reduction and performance improvement. Evaluation results show that our proposed schemes reduce the processor execution time as much as 17% and total computer system energy as much as 5%, respectively. In addition, our effective CPU overclocking schemes reduce the Energy Delay Product (EDP) as much as 22%, on average.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.58-68
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• 2006

This work proposes a 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS A/D Converter (ADC) for high-performance integrated systems such as next-generation DTV and WLAN simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The input SHA maintains 10b resolution with either gate-bootstrapped sampling switches or nominal CMOS sampling switches. The SHA and two MDACs based on a conventional 2-stage amplifier employ optimized trans-conductance ratios of two amplifier stages to achieve the required DC gain, bandwidth, and phase margin. The proposed signal insensitive 3-D fully symmetric capacitor layout reduces the device mismatch of two MDACs. The low-noise on-chip current and voltage references can choose optional off-chip voltage references. The prototype ADC is implemented in a 0.13um 1P8M CMOS process. The measured DNL and INL are within 0.24LSB and 0.35LSB while the ADC shows a maximum SNDR of 54dB and 48dB and a maximum SFDR of 67dB and 61dB at 200MS/s and 250MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 85mW at 250MS/s at a 1.2V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.