• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.3
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• pp.153-159
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• 2009

A CMOS frequency synthesizer for $5{\sim}6$ GHz UNII-band sub-harmonic direct-conversion receiver has been developed. For quadrature down-conversion with sub-harmonic mixing, octa-phase local oscillator (LO) signals are generated by an integer-N type phase-locked loop (PLL) frequency synthesizer. The complex timing issue of feedback divider of the PLL with large division ratio is solved by using multimodulus prescaler. Phase noise of the local oscillator signal is improved by employing the ring-type LC-tank oscillator and switching its tail current source. Implemented in a $0.18{\mu}m$ CMOS technology, the phase noise of the LO signal is lower than -80 dBc/Hz and -113 dBc/Hz at 100 kHz and 1MHz offset, respect-tively. The measured reference spur is lower than -70 dBc and the power consumption is 40 m W from a 1.8 V supply voltage.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1882-1884
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• 1996

This paper deals with the lightning surge counter. In order to install the effective surge protective devices, it is important to find the parameters of incident surges. For the purpose of observing the occurrence frequency as a parameter of the amplitude of surge, two type surge counters were designed and fabricated. One is operated by surge currents, and the other is operated by surge voltages. The former consists of current sensor, metal oxide varister (MOV), rectifier, capacitor and electromagnetic counter. The latter consists of rectifier, voltage divider, comparator, photo coupler and counter circuit, and is useful for detecting the surge voltages.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2008.05a
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• pp.301-304
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• 2008

This paper presents the experimental results on breakdown characteristics in $N_2$ gas under non-uniform electric fields caused by both the positive and negative lightning impulse voltages. $N_2$ gas have an advantage of eco-friendly and cost reduction, and safety aspects. In order to analyze the impulse pre-breakdown processes in $N_2$ gas, we carried out measurements and observations of the impulse breakdown voltages, pre-breakdown current and luminous signals. They were measured by a voltage divider, a shunt and a photo-multiplier tube, respectively. Additionally, the characteristics of discharge channels were observed by high speed cameras. The breakdown voltages in the positive polarity was lower than those in the negative polarity.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1698-1699
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• 2007

This paper deals with the surge measurement system for low voltage power line of industrial plants. It consists of a capacitive divider, A/D conversion part, signal processing and control part. A FPGA and a DSP board were designed to fast signal processing and control. Also, in order to measure lightning surge and switching surge for a long time, data backup device was applied by using SD memory. A performance of the measurement system was verified through evaluation test using impulse calibration generator.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.7 s.337
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• pp.35-40
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• 2005

This paper proposes a fractional-N phase-locked loop (PLL) frequency synthesizer using the 3rd order ${\Delta}{\sum}$ modulator for 900MHz medium speed wireless link. The LC voltage-controlled oscillator (VCO) is used for the good phase noise property. To reduce the lock-in time, a charge pump has been developed to control the pumping current according to the frequency steps and the reference frequency is increased up to 3MHz. A 36/37 fractional-N divider is used to increase the reference frequency of the phase frequency detector (PFD) and to reduce the minimum frequency step simultaneously. A 3rd order ${\Delta}{\sum}$ modulator has been developed to reduce the fractional spur VCO, Divider by 8 Prescaler, PFD and Charge pump have been developed with 0.25um CMOS, and the fractional-N divider and the third order ${\Delta}{\sum}$ modulator have been designed with the VHDL code, and they are implemented through the FPGA board of the Xilinx Spartan2E. The measured results show that the output power of the PLL is about -lldBm and the phase noise is -77.75dBc/Hz at 100kHz offset frequency. The minimum frequency step and the maximum lock-in time are 10kHz and around 800us for the maximum frequency change of 10MHz, respectively.

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.1995-2003
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• 2014

Power semiconductor devices have been the major backbone for high-power electronic devices. One of important parameters in view of power semiconductor devices often characterize with a high breakdown voltage. Therefore, many efforts have been made, since the development of the Insulated Gate Bipolar Transistor (IGBT), toward having higher level of breakdown voltage, whereby the typical design thereof is focused on the structure using the field ring. In this study, in an attempt to make up more optimized field-ring structure, the characteristics of the field ring were investigated with the use of theoretical arithmetic model and methodologically the design of experiments (DOE). In addition, the IGBT having the field-ring structure was designed via simulation based on the finding from the above, the result of which was also analyzed. Lastly, the current study described the trench field-ring structure taking advantages of trench-etching process having the improved field-ring structure, not as simple as the conventional one. As a result of the simulation, it was found that the improved trench field-ring structure leads to more desirable voltage divider than relying on the conventional field-ring structure.

• ETRI Journal
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• v.40 no.5
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• pp.664-676
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• 2018

Given the rapidly increasing market penetration of photovoltaic (PV) systems in many fields, including construction and housing, the effective maintenance of PV systems through remote monitoring at the panel level has attracted attention to quickly detect faults that cause reductions in yearly PV energy production, and which can reduce the whole-life cost. A key point of PV monitoring at the panel level is cost-effectiveness, as the installation of the massive PV panels that comprise PV systems is showing rapid growth in the market. This paper proposes an implementation method that involves the use of a panel-level wireless PV monitoring module (WPMM), and which assesses the cost-effectiveness of this approach. To maximize the cost-effectiveness, the designed WPMM uses a voltage-divider scheme for voltage metering and a shunt-resistor scheme for current metering. In addition, the proposed method offsets the effect of element errors by extracting calibration parameters. Furthermore, a design method is presented for portable and user-friendly PV monitoring, and demonstration results using a commercial 30-kW PV system are described.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.12
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• pp.2933-2938
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• 2014

In this paper, the FLL(Frequency Locked Loop) circuit using current conveyor circuit is designed by $0.35{\mu}m$ CMOS process. The FLL circuit is built in a frequency divider, a frequency-to-voltage converter, a voltage subtractor and a oscillator and the circuit blocks have a symmetric structure to improve a reliability characteristics with a process variation. From the simulation results, the variation rate of output frequency is about less than ${\pm}1%$ when the channel length, channel width, resistance and capacitance are varied ${\pm}5%$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.1-8
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• 2009

In this paper, a temperature variation-insensitive power-up detector for use in analog and digital integrated systems has been proposed. To provide temperature-insensitive characteristic, nMOS and pMOS voltage dividers in the proposed power-up detector are made to have zero temperature coefficient by exploiting the fact that the effective gate-source voltage of a MOS transistor can result in mutual compensation of mobility and threshold voltage for temperature independency. Comparison results using a 68-nm CMOS process indicate that the proposed power-up detector achieves as small as 4 mV voltage variation at 1.0 V power-up voltage over a temperature range of $-30^{\circ}C$ to $90^{\circ}C$, resulting in 92.6% reduction on power-up voltage variations over conventional power-up detectors.

• Journal of Sensor Science and Technology
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• v.5 no.3
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• pp.9-16
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• 1996

This paper deals with the capacitive voltage divider which can measure a transient voltages generated by operating a high voltage impulse generator. The transient voltage measuring system using the capacitive electric field sensor consists of the planar-type electric field sensor having a fast response characteristic and the wide-bandwidth voltage follower, and the input impedance of which is extremely high, about $10^{12}{\Omega}$. In order to analyze the response characteristics to a step input, the newly developed calibration method is proposed, and the error of voltage dividing ratio associated with set-up condition is investigated. Also the optimal set-up condition that is to be maintained within the range of 0.5 % is taken. From the calibration experiment, the frequency bandwidth of the transient voltage measuring system whose response time to a step input is about 15.8 ns, is from 6.37 Hz to 27.3 MHz. Therefore it is possible to measure the commercial frequency voltages as well as the transient over voltages without signal distortions.