• Title/Summary/Keyword: Voltage Divider

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Capacitive Voltage Divider for a Pulsed High-Voltage Measurement (펄스형 고전압 측정용 용량성 전압 분배기)

  • Jang, S.D.;Oh, J.S.;Son, Y.G.;Cho, M.H.
    • Proceedings of the KIEE Conference
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    • 2001.07c
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    • pp.1612-1615
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    • 2001
  • 포항 방사광 가속기 2.5 GeV의 전자선형 가속기는 마이크로웨이브 발생원으로써 80 MW 클라이스트론(klystron) 11대와 입사부에 65 MW 클라이스 트론 1대를 사용한다. 전자빔 에너지의 효율적인 제어를 위하여 고출력 클라이스트론의 RF 전력과 입력 빔의 전력을 정확하게 측정해야 하며 응답특성이 양호한 측정장치와 정밀한 측정이 요구된다. 클라이스트론에 공급되는 전력은 캐소드에 인가되는 전압과 전류의 측정치로 계산된다. 비록 빔 전압측정에서의 작은 오차일지라도 클라이스트론 RF 출력 전력의 결과값에 큰 영향을 미친다. 따라서, 빔 전압의 측정시에 정확한 측정을 위하여 특별한 주의가 요구된다. 고전압 펄스전원장치 인 모듈레이터 (modulator)에서 발생되는 수백 kV(350-400 kV)의 전압을 측정하기 위하여 커패시터의 용량비로 입력전압을 분압하는 용량성 분압기(capacitive voltage divider, CVD)가 사용된다. 고압측 분압용 표준 콘덴서의 정전용량을 결정하는 주요인자는 고전압 절연유의 유전율(dielectric constant)이다. 그러므로, 측정범위 내의 전압, 주파수, 온도에 대하여 정전용량의 변화율이 작도록 설계하여야 한다. 본 논문에서는 펄스형 고전압 신호 측정을 위한 용량성 전압 분배기의 측정원리, 설계분석, 교정시험, 절연유의 온도변화에 따른 정전용량 변화 특성에 대한 실험 결과를 고찰하고자 한다.

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A study on the OLED multi channel DC-DC converter (OLED multi-channel DC-DC converter에 관한 연구)

  • Kim, Jung-Hoon;Park, Seong-Jun;Kim, Jin-Young;Park, Hae-Yeong;Jeong, Jong-Jin;Kim, Hee-Je
    • Proceedings of the KIEE Conference
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    • 2005.07c
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    • pp.2427-2429
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    • 2005
  • OLED in the spotlight of display market has advantages of low power driving, self-emission and fast response. But it has disadvantages of inefficient luminescence and high power consumption. Most of PM(passive Matrix) DC-DC converters in common use is using voltage divider. This voltage divider type has some difficulties of suitable electric device selection for voltage division and of the stabilized output due to feedback current trimming. Therefore, noise analysis and power solution in OLED are important technologies having an effect on electric characteristics. In this dissertation, we have obtained the stable output by using digital signals in multi-channel DC-DC converter, the profit of power consumption reduction of driving source and economical efficiency in the PCB board size.

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Bandwidth Broadening for the GPS Microstrip Patch Antenna (GPS용 마이크로스트립 패치안테나의 광대역화)

  • Son, Taeho
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.14 no.4
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    • pp.73-79
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    • 2015
  • Enhanced bandwidths of the GPS microstrip patch antennas applied by a Wilkinson power divider and a quadrature hybrid were compared. The square patch was designed, and fed by the two port probes for the circuit application. The Wilkinson power divider and quadrature hybrid circuit were designed, and applied to the patch antenna. The designed patch and two circuits were implemented on the FR4 board, and combined together. The measurement of the bandwidth within a voltage standing wave ratio (VSWR) of 2: 1 were 36.5% (1,200~1,775 MHz) in the case of the Wilkinson power divider and 29.84% (1,230~1,700 MHz) in the case of the quadrature hybrid. Axial ratios (AR) in 3dB were 17.14% bandwidth (1,360~1,630 MHz) and 15.87% bandwidth (1,400~1,650 MHz), respectively. The application of the Wilkinson power divider is wider than that of the quadrature hybrid. The peak gains in the anechoic chamber at the GPS center frequency were measured as 2.84 dBi and 2.75 dBi, respectively.

A 54-GHz Injection-Locked Frequency Divider Based on 0.13-㎛ RFCMOS Technology (0.13-㎛ RFCMOS 공정 기반 54-GHz 주입 동기 주파수 분주기)

  • Seo, Hyo-Gi;Yun, Jong-Won;Rieh, Jae-Sung
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.22 no.5
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    • pp.522-527
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    • 2011
  • In this work, a 54 GHz divide-by-3 injection-locked frequency divider(ILFD) based on ring oscillator has been developed in a 0.13-${\mu}M$ Si RFCMOS technology for phase-locked loop(PLL) application. The free-running frequency is 18.92~19.31 GHz with tuning range of 0~1.8 V, consuming 70 mW with a 1.8 V supply voltage. At 0 dBm input power, the locking range is 1.02 GHz(54.82~55.84 GHz) and, with varactor tuning of 0~1.8 V, the total operating range is 2.4 GHz(54.82~57.17 GHz). The fabricated circuit size is 0.42 mm${\times}$0.6 mm including probing pads and 0.099 mm${\times}$0.056 mm for core area.

Voltage regulator for baseband channel selection filters (기저대역 채널선택 필터를 위한 전압 안정화 회로)

  • Kim, Byoung-Wook;Kim, Dae-Ik
    • The Journal of the Korea institute of electronic communication sciences
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    • v.8 no.11
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    • pp.1641-1646
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    • 2013
  • Control voltage for baseband channel selection filter to select one of communication channels can be easily fluctuated according to external noise or variation of fabrication. In this paper, we design a voltage regulator with small chip area to keep control voltage constantly using current comparative method. Cut-off frequency of channel selection filter is automatically controlled by detecting current flow using the proposed voltage regulator.

Precision Measurement Technique of DC Voltage/Resistance Ratio (직류 전압/저항 비율 초정밀 측정기술)

  • Kim, Kyu-Tae;Yu, Kwang-Min
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.51 no.3
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    • pp.96-99
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    • 2002
  • We developed 1:1 resistance ratio measurement system for precision measurement of a series-resistor type dc voltage divider. By using active guard technique and exchange technique, any leakage effects, which are one of the most critical error sources, were successfully removed. The best measurement uncertainty with the developed ratio measurement system was estimated to be approximately $10^{-8}\;for\;10\;k{\Omega}\;and\;100\;k{\Omega}$.

Design of CMOS Dual-Modulus Prescaler and Differential Voltage-Controlled Oscillator for PLL Frequency Synthesizer (PLL 주파수 합성기를 위한 dual-modulus 프리스케일러와 차동 전압제어발진기 설계)

  • Kang Hyung-Won;Kim Do-Kyun;Choi Young-Wan
    • 한국정보통신설비학회:학술대회논문집
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    • 2006.08a
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    • pp.179-182
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    • 2006
  • This paper introduce a different-type voltage-controlled oscillator (VCO) for PLL frequency synthesizer, And also the architecture of a high speed low-power-consumption CMOS dual-modulus frequency divider is presented. It provides a new approach to high speed operation and low power consumption. The proposed circuits simulate in 0.35 um CMOS standard technology.

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New Configuration of a PLDRO with an Interconnected Dual PLL Structure for K-Band Application

  • Jeon, Yuseok;Bang, Sungil
    • Journal of electromagnetic engineering and science
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    • v.17 no.3
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    • pp.138-146
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    • 2017
  • A phase-locked dielectric resonator oscillator (PLDRO) is an essential component of millimeter-wave communication, in which phase noise is critical for satisfactory performance. The general structure of a PLDRO typically includes a dual loop of digital phase-locked loop (PLL) and analog PLL. A dual-loop PLDRO structure is generally used. The digital PLL generates an internal voltage controlled crystal oscillator (VCXO) frequency locked to an external reference frequency, and the analog PLL loop generates a DRO frequency locked to an internal VCXO frequency. A dual loop is used to ease the phase-locked frequency by using an internal VCXO. However, some of the output frequencies in each PLL structure worsen the phase noise because of the N divider ratio increase in the digital phase-locked loop integrated circuit. This study examines the design aspects of an interconnected PLL structure. In the proposed structure, the voltage tuning; which uses a varactor diode for the phase tracking of VCXO to match with the external reference) port of the VCXO in the digital PLL is controlled by one output port of the frequency divider in the analog PLL. We compare the proposed scheme with a typical PLDRO in terms of phase noise to show that the proposed structure has no performance degradation.

Analysis of PLL Phase Noise Effect for High Data-rate Underwater Communications

  • Lee, Chong-Hyun;Bae, Jin-Ho;Hwang, Chang-Ku;Lee, Seung-Wook;Shin, Jung-Chae
    • International Journal of Ocean System Engineering
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    • v.1 no.4
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    • pp.205-210
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    • 2011
  • High data-rate underwater communications is demanded. This demand imposes stringent requirements on underwater communication equipment of phase-locked-loop (PLL). Phase noise in PLL is unwanted and unavoidable. In this paper, we investigate the PLL phase noise effect on high order QAM for underwater communication systems. The phase noise model using power spectral density is adopted for performance evaluation. The phase noise components considered in PLL are reference oscillator, voltage controlled oscillator (VCO), filter and divider. The filters in PLL noise are assumed to be second order active and passive low pass filters. Through simulation, we analyze the phase noise characteristics of the four components and then investigate the performance improvement factor of each component. Consequently, we derive specifications of VCO, phase detector, divider to meet performance requirement of high data-rate communication using QAM under phase noise influence.

A Study on the Compensation Method in the Measuring System for Chopped Lightning Impulse (충격전압 재단과 측정을 위한 보상회로에 관한 연구)

  • Kim, Ik-Soo;Kim, Young-Bae;Kim, Jin-Gi;Kim, Min-Kyu
    • Proceedings of the KIEE Conference
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    • 1996.07c
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    • pp.1895-1897
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    • 1996
  • Lightning impulse voltage is essential to evaluate the insulation performance of electric power apparatus. Recently international standard (IEC-60) on high voltage measurement techniques are being revised. In the draft of this standard, a new calibration method is introduced and the accuracy of most industrial measuring systems is maintained by means of comparison test against the reference measuring systems. Comparison tests of dividers for chopped lightning impulse measurement were rallied out by KERI. The 700kV shielded resisitive divider with and without compensation element were done comparison test with 300kV PTB divider which have the similar charateristics as that were circulated among the laboratories. This paper reports on the calculation results of response charateristics obtained by EMTP and the comparison test results with chopped lightning impulse voltages from 150kV to 250kV. It is demonstrated that KERI are capable of realizing the idea in the revision of the IEC standand, that is, to establish traceability.

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