• Title/Summary/Keyword: Voltage Application Time

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Application-Level Energy Optimization Technique for Video Applications with Video Quality Constraint (비디오 응용에서 화질 제약을 고려한 응용 수준의 에너지 최적화 기법)

  • 임채석;하순회
    • Proceedings of the Korean Information Science Society Conference
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    • 2003.04a
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    • pp.151-153
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    • 2003
  • 이 논문은 프레임 기반의 비디오 응용에 대해서 화질 (video quality) 제약을 고려한 응용 수준(application-level)에서의 에너지 최적화 기법을 제안한다. 화질과 에너지 소모 사이에는 상관관계 (trade-off)가 있음을 이용하여. 본 논문은 H.263 인코더의 화질을 실시간으로 모니터링해서 프레임 속도(frame rate)를 자동으로 조절하는 알고리즘을 제안한다. 기존 동적 전압 스케줄링 (DVS: dynamic voltage scheduling) 기법은 유휴 시간 (slack time)을 주어진 것이라고 가정하는 반면, 제안하는 기법은 유휴 시간 자체를 증가시켜서 DVS 기법의 효과를 향상시킨다. 제안하는 기법이 주어진 화질 제약을 만족하며 상당한 에너지 소모를 감소함을 실험을 통해서 알 수 있다.

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A 6.4-Gb/s/channel Asymmetric 4-PAM Transceiver for Memory Interface

  • Lee, Kwang-Hun;Jang, Young-Chan
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2011.05a
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    • pp.129-131
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    • 2011
  • An 6.4-Gb/s/channel 4-PAM transceiver is designed for a high speed memory application. The asymmetric 4-PAM signaling scheme is proposed to increase the voltage and time margins, and reduces the reference noise effect in a receiver by 33%. To reduce ISI in a channel, 1-tap pre-emphasis of a transmitter is used. The proposed asymmetric 4-PAM transceiver was implemented by using 0.13um 1-poly 6-metal CMOS process with 1.2V supply. The active area and power consumption of 1-charmel transceiver including a PLL are $0.294um^2$ and 6mW, respectively.

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Planar-type Sensor for Measuring the Time-varying Electric Fields (시변전장 측정용 평판형 센서)

  • Lee, Bok-Hee;Kil, Gyung-Suk
    • Journal of Sensor Science and Technology
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    • v.4 no.1
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    • pp.15-20
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    • 1995
  • This paper deals with the planar-type sensor which can measure the time-varying electric fields. To make an electric field measurement system having a wide bandwidth, a planar-type sensor is proposed. The theoretical principle and design rule of the measuring device are introduced, and also the calibration and application investigations are carried out. From the calibration experiments, the frequency bandwidth of the electric field measurement device ranges from 160 [Hz] to 25 [MHz] and the sensitivity of the sensor is 1.2 [mV/V/m]. As the application experiments, the electric fields caused by the impulse and oscillating transient voltage in high voltage laboratory are measured by the proposed device, and the results are excellent.

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Design and Test Results of High-Power Pulse Generator System for Industrial Accelerator Application (산업용 가속기용 고출력 펄스시스템의 설계와 시험)

  • Jang, S.D.;Kim, S.H.;Yang, H.Y.;Cho, M.H.;Ko, I.S.;NamKung, W.
    • Proceedings of the KIEE Conference
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    • 2009.07a
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    • pp.1370_1372
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    • 2009
  • A conventional linear accelerator system requires a flat-topped pulse with less than $\pm$ 0.5% ripple to meet the beam energy spread requirements and to improve pulse efficiency of RF systems. A a line-type pulsed modulator is widely used in pulsed power circuits for applications such as accelerators, radar, medical radiation, or ionization systems. The high-voltage pulse generator system with an output voltage of 284 kV, a pulse width of $10{\mu}s$, and a rise time of $0.84{\mu}s$ has been designed and fabricated to drive a klystron which has 30-MW peak and 60-kW average RF output power. The high-voltage test was performed using the klystron load. This thesis describes the design and test results of high-power pulse generator system for industrial accelerator application. The experimental results were analyzed and compared with the design.

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Mechanism and Application of NMOS Leakage with Intra-Well Isolation Breakdown by Voltage Contrast Detection

  • Chen, Hunglin;Fan, Rongwei;Lou, Hsiaochi;Kuo, Mingsheng;Huang, Yiping
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.13 no.4
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    • pp.402-409
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    • 2013
  • An innovative application of voltage-contrast (VC) inspection allowed inline detection of NMOS leakage in dense SRAM cells is presented. Cell sizes of SRAM are continual to do the shrinkage with bit density promotion as semiconductor technology advanced, but the resulting challenges include not only development of smaller-scale devices, but also intra-devices isolation. The NMOS leakage caused by the underneath n+/P-well shorted to the adjacent PMOS/N-well was inspected by the proposed electron-beam (e-beam) scan in which VC images were compared during the in-line process step of post contact tungsten (W) CMP (Chemical Mechanical Planarization) instead of end-of-line electrical test, which has a long response time. A series of experiments based on the mechanism for improving the intra-well isolation was performed and verified by the inline VC inspection. An optimal process-integration condition involved to the tradeoff between the implant dosage and photo CD was carried out.

Fault Angle Dependent Resistance of YBCO Coated Conductor with Stainless Steel Stabilizer Layer

  • Du, Ho-Ik;Kim, Min-Ju;Doo, Seung-Gyu;Kim, Yong-Jin;Han, Byoung-Sung
    • Transactions on Electrical and Electronic Materials
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    • v.10 no.2
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    • pp.66-69
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    • 2009
  • To manufacture YBCO-coated conductors as superconducting fault current limiters, it is important to conduct researches on their durability. To test their durability, it is necessary to investigate their properties before and after the quench in more severe conditions than in general operating conditions. In this study, their voltage-current and resistance properties were measured before and after a fault current was repetitively applied to them. For the applied voltage, the voltage grades of the YBCO coated conductors were considered. The current amplitude was controlled using protective resistance on an experimental track, and the time and number of applications were fixed to produce the quench occurrence at the fault angles of $0^{\circ}$, $45^{\circ}$, and $90^{\circ}$. The operating conditions of the YBCO coated conductors as the main components of superconducting fault current limiters were determined using their voltage properties. The voltage properties of the YBCO coated conductors that were analyzed in this research will be used as important data for their practical application to superconducting fault current limiters.

Design Optimization of High-Voltage Pulse Transformer for High-Power Pulsed Application (고출력 펄스응용을 위한 고전압 펄스변압기 최적설계)

  • Jang, S.D.;Kang, H.S.;Park, S.J.;Han, Y.J.;Cho, M.H.;NamKung, W.
    • Proceedings of the KIEE Conference
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    • 2008.07a
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    • pp.1297-1300
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    • 2008
  • A conventional linear accelerator system requires a flat-topped pulse with less than ${\pm}$ 0.5% ripple to meet the beam energy spread requirements and to improve pulse efficiency of RF systems. A pulse transformer is one of main determinants on the output pulse voltage shape. The pulse transformer was investigated and analyzed with the pulse response characteristics using a simplified equivalent circuit model. The damping factor ${\sigma}$ must be >0.86 to limit the overshoot to less than 0.5% during the flat-top phase. The low leakage inductance and distributed capacitance are often limiting factors to obtain a fast rise time. These parameters are largely controlled by the physical geometry and winding configuration of the transformer. A rise time can be improved by reducing the number of turns, but it produces larger pulse droop and requires a larger core size. By tradeoffs among these parameters, the high-voltage pulse transformer with a pulse width of 10 ${\mu}s$, a rise time of 0.84 ${\mu}s$, and a pulse droop of 2.9% has been designed and fabricated to drive a klystron which has an output voltage of 284 kV, 30-MW peak and 60-kW average RF output power. This paper describes design optimization of a high-voltage pulse transformer for high-power pulsed applications. The experimental results were analyzed and compared with the design. The design and optimal tuning parameter of the system was identified using the model simulation.

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Dynamic Voltage Scaling Technique Considering Application Characteristics (응용 프로그램 특성을 고려한 동적 전압 조절 기법)

  • Cho, Young-Jin;Chang, Nae-Hyuck
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.12
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    • pp.96-104
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    • 2009
  • In the real system environments, the performance of the application is not linearly proportional to the clock frequency of the microprocessor, in contrast to the general assumption of conventional dynamic voltage scaling. In this paper, we analytically model the relation between the performance of the application and the clock frequency of the microprocessor, and introduce the energy-optimal scheduling algorithm for a task set with distinct application characteristics. In addition, we present a theorem for the energy-optimal scheduling, which the derivative of the energy consumption with respect to the execution time should be the same for all the tasks. The proposed scheduling algorithm always generates the energy-optimal scaling factor thanks to the theorem for energy-optimal scheduling. We achieved about 7% additional energy reduction in the experiments using synthetic task sets.

Pspice Simulation for Nonlinear Components and Surge Suppression Circuits (비선형 소자 및 서지억제회로의 Pspice 시뮬레이션)

  • Lee, Bok-Hui;Gong, Yeong-Eun;Choe, Won-Gyu;Jeon, Deok-Gyu
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.49 no.8
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    • pp.477-486
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    • 2000
  • This paper presents Pspice modeling methods for spark gaps and ZnO varistors and describes the application for the two-stage surge suppression circuit which was composed of the nonlinear components. The simulation modelings of nonlinear components were conducted on the basis of the voltage and current curves measured by the impulse current with the time-to-crest of $1~50 \mus$ and the impulse voltage with the rate of the time-to-crest of 10, 100 and 1000 V/\mus$. The firing voltages of the spark gap increased with increasing the rate of the time-to-crest of impulse voltage and the measured data were in good agreement with the simulated data. The I-V curves of the ZnO varistor were measured by applying the impulse currents of which time-to-crests range from 1 to $50 \mus$ and peak amplitudes from 10 A to 2 kA. The simulation modeling was based on the I-V curves replotted by taking away the inductive effects of the test circuit and leads. The meximum difference between the measured and calculated data was of the order of 3%. Also the two-stage surge suppression circuit made of the spark gap and the ZnO varistor was investigated with the impulse voltage of $10/1000\mus$$mutextrm{s}$ wave shape. The overall agreement between the theoretical and experimental results seems to be acceptable. As a consequence, it was known that the proposed simulation techniques could effectively be used to design the surge suppression circuits combined with nonlinear components.

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Signal Generation Due to Alpha Particle in Hydrogenated Amorphous Silicon Radiation Detectors

  • Kim, Ho-Kyung;Gyuseong Cho
    • Nuclear Engineering and Technology
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    • v.28 no.4
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    • pp.397-404
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    • 1996
  • The hydrogenated amorphous silicon (a-Si : H) holds good promise for radiation detection from its inherent merits over crystalline counterpart. For the application to alpha spectroscopy, the induced charge collection in a-Si : H pin detector diodes ons simulated based on a relevant non-uniform charge generation model. The simulation was peformed for the initial energy and the range of incident alpha particles, detector thickness and the operational parameters such as the applied reverse bias voltage and shaping time. From the simulation, the total charge collection was strongly affected by hole collection as expected. To get a reasonable signal generation, therefore, the hole collection should be seriously considered for detector operational parameters such as shaping time and reverse voltage etc. For the spectroscopy of alpha particle from common alpha sources, the amorphous silicon should have about 70${\mu}{\textrm}{m}$ thickness.

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