• Journal of the Institute of Convergence Signal Processing
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• v.5 no.3
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• pp.223-229
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• 2004

Recently, OFDM and STC techniques have been considered to be candidate to support multimedia services in the next generation mobile radio communications and have been developed the many communications systems in order to achieve the high data rates. In this paper, we propose the Trellis-Coded Differential Space Time Modulation-OFDM system with multiple symbol detection. The Trellis-code performs the set partition with unitary group codes. The Viterbi decoder containing new branch metrics is introduced in order to improve the bit error rate (BER) in the differential detection of the unitary differential space time modulation. Also, we describe the Viterbi algorithm in order to use this branch metrics. Our study shows that such a Viterbl decoder improves BER performance without sacrificing bandwidth and power efficiency.

• The Journal of the Acoustical Society of Korea
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• v.30 no.3
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• pp.149-157
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• 2011

In this paper, we propose a new cardiac disorder classification method using an support vector machine (SVM) to combine hidden Markov model (HMM) and murmur existence information. Using cepstral features and the HMM Viterbi algorithm, we segment input heart sound signals into HMM states for each cardiac disorder model and compute log-likelihood (score) for every state in the model. To exploit the temporal position characteristics of murmur signals, we divide the input signals into two subbands and compute murmur probability of every subband of each frame, and obtain the murmur score for each state by using the state segmentation information obtained from the Viterbi algorithm. With an input vector containing the HMM state scores and the murmur scores for all cardiac disorder models, SVM finally decides the cardiac disorder category. In cardiac disorder classification experimental results, the proposed method shows the relatively improvement rate of 20.4 % compared to the HMM-based classifier with the conventional cepstral features.

• Journal of the Institute of Convergence Signal Processing
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• v.3 no.2
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• pp.53-57
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• 2002

Recently, digital communication system becomes high speed, as communication demand dose not only increases sharply, but an image, voice various kinds data also comes multimedia. In transmitting data at a high speed, the main problem is fading by multipath. A linear or nonlinear distortion arise In multipath channel fading from ISI(Intersymbol Interference). For restoring this distorted signal, A lot of equalizer and adaptive algorithm is introduced. This paper compares and analysises, for improving communication quality in channel which is long delay spread, performance of decision feedback equalizer by RLS algorithm, a channel estimation by RLS-MLSE and viterbi equalizer Particularly, there Is exactly channel estimation of impluse response and excellent property of equalization about channel, which delay spread is long impluse response comparatively and is property of non-minimun phase.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.93-96
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• 2008

This paper describes an efficient design of a multi-standard Viterbi decoder that supports multiple constraint lengths and code rates. The Viterbi decode. is parameterized for the code rates 1/2, 1/3 and constraint lengths 7, 9, thus it has four operation modes. In order to achieve low hardware complexity and low power, an efficient architecture based on hardware sharing techniques is devised. Also, the optimization of ACCS (Accumulate-Subtract) circuit for the one-point trace-back algorithm reduces its area by about 35% compared to the full parallel ACCS circuit. The parameterized Viterbi decoder core has 79,818 gates and 25,600 bits memory, and the estimated throughput is about 105 Mbps at 70 MHz clock frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.10
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• pp.1147-1156
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• 1992

In this paper, in order to apply the $\pi/4$ shift QPSK to TCM, we propose the $\pi/8$ shift 8PSK modulation technique and the trellis-coded $\pi/8$ shift 8PSK performing signal set expansion and partition by phase difference. In addition, the Viterbi decoder with branch metrics of the squared Euclidean distance of the first phase difference as well as the Lth phase different is introduced in order to improve the bit error rate(BER) performance in differential detection of the trellis-coded $\pi/8$ shift 8PSK. The proposed Viterbi decoder is conceptually the same as the sliding multiple detection by using the branch metric with first and Lth order phase difference. We investigate the performance of the uncoded $\pi/4$ shift QPSK and the trellis-coded $\pi/8$ shift 8PSK with or without the Lth phase difference metric in an additive white Gaussian noise (AWGN) using the Monte Carlo simulation. The study shows that the $\pi/4$ shift QPSK with the Trellis-code i.e. the trellis-coded $\pi/8$ shift 8PSK is an attractive scheme for power and bandlimited systems and especially, the Viterbi decoder with first and Lth phase difference metrics improves BER performance. Also, the nest proposed algorithm can be used in the TC $\pi/8$ shift 8PSK as well as TCMDPSK.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.10
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• pp.827-832
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• 2013

Holographic data storage system is affected by two dimensional intersymbol interference and inter-page interference. Especially, for multi-level holographic data storage system, since one pixel contains more than 1 bit, the system is more vulnerable to the error. In this paper, we propose a 2/3 modulation code for 4-level holographic data storage system. The proposed modulation code with error correcting capability could be compensated these interferences. Also, in this paper, we proposed a Viterbi decoder for 2/3 modulation code. The proposed Viterbi decoder eliminates unnecessary calculation. As a result, proposed 2/3 modulation code and Viterbi decoder has shown better performance than conventional one.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.3
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• pp.384-389
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• 2003

A new two-step soft-output Viterbi algorithm (SOVA) decoder architecture is presented. A significant reduction in the decoding latency can be achieved through the use of the dual-port RAM in the survivor memory structure of the trace-back unit. The system complexity can be lowered due to the determination of the absolute value of the path metric differences inside the add-compare-select (ACS) unit. The proposed SOVA architecture was verified successfully by the functional simulation of Verilog HDL modeling and the FPGA prototyping. The SOVA decoder achieves a data rate very close to that of the conventional Viterbi Algorithm (VA) decoder and the resource consumption of the realized SOVA decoder is only one and a half times larger than that of the conventional VA decoder.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.5
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• pp.497-501
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• 2008

In this paper we present a method for continuous EEG classification, where we employ nonnegative tensor factorization (NTF) to determine discriminative spectral features and use the Viterbi algorithm to continuously classily multiple mental tasks. This is an extension of our previous work on the use of nonnegative matrix factorization (NMF) for EEG classification. Numerical experiments with two data sets in BCI competition, confirm the useful behavior of the method for continuous EEG classification.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.11
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• pp.1095-1102
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• 1991

In this paper, we proposed the differential demodulation technique of 2-h CPM and analyzed its error performances. We derived the sets of modulation indices of 2-h phase codes adequate to the differential detection. The power spectra of 2-h CPM signals with various sets of mudulation indices are illustrated and compared, Besides, the error performances for the differential detectors are calculated and detectors using Viterbi algorithm are compared and analyzed by computer simulations.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.05a
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• pp.407-410
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• 1999

Viterbi decoder is implemented with a Radix-4 architecture at 0.5$\mu\textrm{m}$ process even though the delay time of standard tell is big and it causes a bigger chip size. As process develops, the delay time of standard cells is getting smaller. Therefore, the requirement of speed and chip size is satisfied by using Radix-2 algorithm to implement Viterbi decoder.