• Journal of IKEEE
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• v.4 no.2 s.7
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• pp.257-265
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• 2000

Turbo Code decoder is an iterate decoding technology, which extracts extrinsic information from the bit to be decoded by calculating both forward and backward metrics in each decoding step, and uses the information to the next decoding step. Viterbi decoder, which is for a convolutional code, runs continuous mode, while Turbo Code decoder runs by block unit. There are algorithms used in a decoder : which are MAP(maximum a posteriori) algorithm requiring very complicated calculation and SOVA(soft output Viterbi algorithm) using Viterbi algorithm suggested by Hagenauer, and it is known that the decoding performance of MAP is better. The result of this make experimentation shows that the performance of SOVA, which has half complex algorithm compare to MAP, is almost same as the performance of MAP when the SOVA decoding performance is supplemented with Robust equalization techniques.

• Journal of Digital Convergence
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• v.20 no.1
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• pp.185-190
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• 2022

Bluetooth is a common wireless technology that is widely used as a connection medium between various consumer electronic devices. The Bluetooth receiver usually adopts a Viterbi algorithm to improve signal-to-noise ratio performance, but requires complex hardware and calculations for continuous search and estimation for the irrational modulation indexes at the transmission. This paper proposes a non-coherent maximum estimation based 8-State Viterbi FSM to solve these complexity problems. The proposed optimal Viterbi FSM can detect Gaussian frequency-shfit keying symbol without any prior information and estimation for the modulation indexes. The HV1/HV2 packets are used for the estimation of the proposed algorithm and the simulation results have shown performance improvements with about 2dB for 10^-3 BER compared to other ideal approaches such as decision direct method.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.687-690
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• 1998

The full Viterbi detector for EPRML read channel system needs large area due to complex computation. There are several conventional methods to reduce the complexity such as GVA(Generalized Viterbi Algorithm) and BMS(Branch Metric Shift). This paper proposes another method, FVD(Folding Viterbi Detector), that has state transition diagram folded with inverted states. Compared with GVA detector, FVD requires only 61% gates and has lower power consumption and better BER performance.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2003.06a
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• pp.217-221
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• 2003

In this paper, the Viterbi decoder containing new branch metrics of the squared Euclidean distance with multiple order phase differences is introduced in order to improve the bit error rate (BER) in the differential detection of the trellis-coded MDPSK-OFDM. The proposed Viterbi decoder is conceptually same as the multiple Phase differential detection method that uses the branch metric with multiple phase differences. Also, we describe the Viterbi algorithm in order to use this branch metrics. Our study shows that such a Viterbi decoder improves BER performance without sacrificing bandwidth and power efficiency. Also, the proposed algorithm can be used in the single carrier modulation.

• Journal of Advanced Navigation Technology
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• v.8 no.2
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• pp.190-196
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• 2004

The development of a new hardware structure which can implement the viterbi algorithm efficiently is required for applications such as a software radio because the viterbi algorithm, which is an error correction code function for the second and the third generation of mobile communication, needs a lot of arithmetic operations. The length of K in the viterbi algorithm different from each standard, for examples, K=7 in case of IS-95 standard and GSM standard, and K=9 in case of WCDMA and CDMA2000. In this paper, we propose a new hardware structure of an adaptive viterbi decoder which can decode the constraint length in K=3~9 and the data rate in 1/2 ~ 1/3. Prototyping results targeted to Altera Cyclon EPIC20F400C8, shows that the proposed hardware structure needs maximum 19,276 logic elements and power dissipation of 222.6 mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.277-284
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• 2001

Viterbi algorithm is widely used in digital communication system for FEC(forward error correction). Each communication systems based on the Viterbi algorithm use specific Viterbi decoder which has different code parameter values. Even if Viterbi decoder has the same code parameters, it can be varied by the design architecture adopted. We propose the parameterized VHDL model generator for the efficiency of the design. It makes it possible to achieve shorter design time and lower design cost. The model generator searches the design space available and finds out the optimal design point to generate a decoder model.

• The KIPS Transactions:PartA
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• v.12A no.1 s.91
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• pp.1-6
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• 2005

This paper presents a new algorithm on low power survivor path memory implementation of the trace-back systolic array Viterbi algorithm. A novel idea is to reuse the already-generated trace-back routes to reduce the number of trace-back operations. And the spurious switching activity of the trace-back unit is reduced by making use of a clock gating method. Using the SYNOPSYS power estimation tool, DesignPower, our experimental result shows the average $40{\%}$ power reduction and $23{\%}$ area increase against the trace-back unit introduced in [1].

• Journal of the Korean Institute of Intelligent Systems
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• v.14 no.5
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• pp.583-586
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• 2004

Transition jitter noise is one of major sources of detection errors in high density recording channels. Implementation complexity of the optimal detector for such channels is high due to the data dependency and correlated nature of the jitter noise. In this paper, two types of hardware efficient sub-optimal detectors are derived by modifying branch metric of Viterbi algorithm and applied to partial response (PR) channels combined with run length limited modulation coding. The additional complexity over the conventional Viterbi algorithm to incorporate the modified branch metric is either a multiplication or an addition for each branch metric in the Viterbi trellis.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39A no.3
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• pp.121-126
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• 2014

Demand of the data storage becomes more and more growing. This requests the next generation of storage devices to have the dominated storage capability associated with superfast read/write rate. Holographic data storage (HDS) is investigated for a long time and is considered to be a candidate for the future storage system. However, it has two-dimensional intersymbol interference that conventional one-dimensional detection solutions have not yet handled strictly because of the complexity level of system as well as the cost. We propose a new scheme that combines iterative soft output Viterbi algorithm with noise filter for improving the bit error rate performance of HDS.

• The Journal of the Acoustical Society of Korea
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• v.13 no.2E
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• pp.58-67
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• 1994

Hidden Markov Model (HMM)-based algorithms have been used successfully in many speech recognition systems, especially large vocabulary systems. Although general purpose processors can be employed for the system, they inevitably suffer from the computational complexity and enormous data. Therefore, it is essential for real-time speech recognition to develop specialized hardware to accelerate the recognition steps. This paper concerns with a real-time implementation of an isolated word recognition system based on HMM. The speech recognition system consists of a host computer (PC), a DSP board, and a prototype Viterbi scoring board. The DSP board extracts feature vectors of speech signal. The Viterbi scoring board has been implemented using three field-programmable gate array chips. It employs a hardware-efficient Viterbi scoring architecture and performs the Viterbi algorithm for HMM-based speech recognition. At the clock rate of 10 MHz, the system can update about 100,000 states within a single frame of 10ms.