• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4A
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• pp.539-545
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• 2000

A 40-Mb/s, 64-state, R= 1/2, 3 bit soft decision Viterbi decoder based on Radix-4 method has been designed and fabricated using a FLEX10K CPLD chip in this paper. In order to implement the high-speed Viterbi decoder, the architectures of adder-compare-select(ACS), branch metric calculation(BMC), trace back(TB) are present. In practical designed by ASIC, the speed is faster than that of CPLD by 6~7 times. Therefore, 40 Mb/s Viterbi decoder architecture can be used for high-speed wireless multimedia communications with 200 Mb/s.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.58 no.4
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• pp.623-626
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• 2009

In this paper, we applied new analog viterbi decoder to decode PR(1,2,2,1) signal for DVD and analyze the specific and signal characteristics. We implemented the parallel analog viterbi decoder and the convolution digital viterbi decoder(the digital PRML) utilizing the technology of analog parallel processing circuits. The proposed analog viterbi decoder can replace the conventional digital viterbi decoder by a new one. Our circuits design the low distortion and the high accuracy over the previous implementation. Through the parallel structure of the proposed viterbi decoder, we got the achievement of the decoding speed by the multiple times.

• The KIPS Transactions:PartC
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• v.13C no.1 s.104
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• pp.75-82
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• 2006

In this paper, a space-frequency coded orthogonal frequency division multiplexing (SFC-OFDM) scheme with dual Viterbi decoder is proposed and analyzed. Here, two independent half-rate OFDM symbols are generated after convolutional coding of the binary source code. A dual Viterbi decoder is exploited to decode the demodulated sequences independently in the receiver, and their path metrics are compared. Accordingly, the recovered binary data in the proposed scheme are composed of the combination of the sequences having larger path metrics while those in a conventional system are simply the output of single Viterbi decoder. As a result, the proposed SFC-OFDM scheme has a better performance than the conventional one for all signal-to-noise power ratio.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1939-1940
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• 2008

1967년 Andrew J. Viterbi에 의해 처음 제안된 Viterbi 알고리즘은 길쌈부호(convolution code)의 대표적인 복호방법으로 현재 통신 기술 중에서 가장 많이 쓰이는 것 중에 하나이다. Viterbi decoder는 사용되는 시스템의 사양에 따라 에러 수정 능력이 다른데 통신 channel 상의 오류뿐만 아니라 Viterbi decoder내부에 있는 메모리에서 발생하는 오류도 Viterbi decoder의 에러 수정 능력에 영향을 준다. 본 논문에서는 일반적으로 많이 확인되었던 channel상의 오류와 함께 Viterbi decoder내부에 있는 메모리에서 오류가 발생했을 때 복.부호기의 사양에 따른 에러정정능력을 분석하였다.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.1
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• pp.1-11
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• 1999

In this paper, we proposed a design method of parameterized viterbi decoder, which automatically synthsizes the diverse viterbi deciders used in the digital mobile communication systems. It is designed to synthesize a viterbi decoder specified by user-provided parameters. Those parameters are constraint length, code rate generator polynomials of teh convolutional encoder, data rate and bits/frame of the data transmission, and soft decision bits of viterbi decoder. For the design of the parameterized viterbi decoder, we designed a user interface module C-language, and a viterbi decoder module in a hierarchical atructure using VHDL language and its generic statement. For the verification of the parameterized viterbi decoder, we compared our synthesized viterbi decoder with the conventional viterbi decoder which is designed for the IS-95 CDMA system. The proposed design method of the viterbi decoder will be a new method to obtain a required viterbi decoder in a very short time only by supplying the design parameters.

• The Journal of the Acoustical Society of Korea
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• v.13 no.2E
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• pp.58-67
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• 1994

Hidden Markov Model (HMM)-based algorithms have been used successfully in many speech recognition systems, especially large vocabulary systems. Although general purpose processors can be employed for the system, they inevitably suffer from the computational complexity and enormous data. Therefore, it is essential for real-time speech recognition to develop specialized hardware to accelerate the recognition steps. This paper concerns with a real-time implementation of an isolated word recognition system based on HMM. The speech recognition system consists of a host computer (PC), a DSP board, and a prototype Viterbi scoring board. The DSP board extracts feature vectors of speech signal. The Viterbi scoring board has been implemented using three field-programmable gate array chips. It employs a hardware-efficient Viterbi scoring architecture and performs the Viterbi algorithm for HMM-based speech recognition. At the clock rate of 10 MHz, the system can update about 100,000 states within a single frame of 10ms.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.375-377
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• 2006

A Analog parallel processing-based Viterbi decoder which decodes PRML signal of DVD has been designed by CMOS circuit. The analog processing-based Viterbi decoder implements are functions of the conventional digital Viterbi decoder utilizing the analog parallel processing circuit technology. The Analog parallel processing-based Viterbi decoding technology is applied for the PR(1,2,2,1) signal decoding of DVD. The benefits are low power consumption and less silicon consumption. In this paper, the comparison of the Analog parallel processing-based Viterbi Decoder which has a function of the error correction between Max operation and Average operation is discussed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.4
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• pp.831-837
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• 1999

본 논문에서는 Viterbi 복호기의 동작을 고속화할 수 있는 구조를 제시하였고, 제시된 방식으로 설계된 Viterbi 복호기를 CPLD 칩으로 구현하였다. Altera사의 Design Compiler를 이용하여 FLEX10K 칩에 합성한 Viterbi 복호기는 최고 20[Mbps]급 전송속도를 갖고 있으며, ASIC 설계시 100Mbps 이상의 속도가 가능하므로 고속 무선멀티미디어통신 시스템의 오류정정부호로 적용될 수 있다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.6C
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• pp.601-609
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• 2002

The efficient Viterbi decoder that supports full data-rate output of DAB system was proposed. Viterbi decoder consumes lots of computational load and should be designed to be fast specific hardware. In this paper, SST scheme was adopted for Viterbi decoder with puncturing to reduced the power consumption. Puncturing vector tables are modified and re-arranged to be designed by a hardwired logic to save the system area. New re-scaling scheme which uses the fact that the difference of the maximum and minimum of the path metric values is bounded is proposed. The proposed re-scaling scheme optimizes the wordlength of path metric memory and greatly reduces the computational load for re-scaling by controlling MSB of path metric memory. Another saving of computation is done by proposed algorithm for branch metric calculation, which makes use of pre-calculated metric values. The designed Viterbi decoder was synthesized using SAMSUNG 0.35$\mu$ standard cell library and occupied small area and showed lower power consumption.

• ETRI Journal
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• v.35 no.5
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• pp.767-774
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• 2013

In this paper, a novel parallel Viterbi decoding scheme is proposed to decrease the decoding latency and power consumption for the software-defined radio (SDR) system. It implements a divide-and-conquer approach by first dividing a block into a series of subblocks, then performing independent Viterbi decoding for each subsequence, and finally merging the surviving subpaths into the final path. Moreover, a network-on-chip-based SDR platform is used to evaluate the performance of the proposed parallel Viterbi decoding scheme. The experiment results show that our scheme can speed up the Viterbi decoding process without increasing the BER, and it performs better than the current state-of-the-art methods.