• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.10
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• pp.1617-1623
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• 1989

The introduction of the fast Fourier transform(FFT),an efficient computational algorithm for the discrete Fourier transform(DFT) by Cooley and Tukey(1965), has brought to the limelight various other discrete transforms. Some of the analog functions from which these transforms have been derived date back to the early 1920's, for example, Walsh functions (Walsh, 1923) and Hadamard Transform(Enomoto et al, 1965). Fast algorithms developed for the forward transform are equally applicable, exept for minor changes, to the inverse transform. In this paper, we present a simple pipelined Hadamard matrix(HM) which is used to develop a fast algorithm for the Hadamard Processor (HP). The Fast Hadamard Transform(FHT) can be derived using matrix partitioning techniques. The HP system is incorporated through a modular design which permits tailoring to meet a wide range of video data link applications. Emphasis has been placed on a low cost, a low power design suitable for airbone system and video codec.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.561-564
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• 2009

This paper present design and implementation of U-city infrared image surveillance system based on the digital media processor. The hardware is designed and implemented by using commercial chips such as DM642 processor and video encoder, video decoder and the functions of software are to analyze temperature distribution of a monitoring image and to monitor disaster situation such as fire. The required functions and performances are confirmed by testing of the prototype and we verified practicality of the system.

• Proceedings of the KIEE Conference
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• 1990.11a
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• pp.439-442
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• 1990

A powerful general purpose image processing processor is developed using a high-speed DSP chip, TMS320C30. The image processing processor, compatible to the standard VME bus, is composed of VME bus interface unit, video rate image grabbing/coding unit, TMS320C30 interface unit and bank of high-speed SRAMs. The performance is evaluated experimentally with the general image processing algorithms and the results show that the developed processor is capable of high speed image processing.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.306-309
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• 2008

A system realization for video surveillance with interframe probability distribution analysis is presented in this paper. The system design is based on a high performance DSP processor, video surveillance is implemented by analyzing interframe probability distribution for scanning objects in a restricted area and the video analysis algorithm is decided for forming a different image from the probability distribution of several frames compressed by the standardized JPEG. The algorithm processing time of D1($720{\times}480$) image per frame is 85ms.

• Proceedings of the KSR Conference
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• 1999.11a
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• pp.259-266
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• 1999

A study on the static type train simulator will include the training of new drives requires that the environment of the cab, controls placement, etc. must highly realistic so that driver can readily transfer his training experience to the real world. The simulator computer sends video disc speed command to a Video PC processor. A video switcher select the output of the on-line player. This selection is done with loss of vertical synchronization, meaning the picture will not noticeable roll or jump as the simulation mover from disc to disc. The video image quality remain contestant through the simulated speed range from zero to 100km/h. Flicker is avoided in the scene by the use of a TBC(Time Base Corrector) which causes the display of one video field at a time. Thus, no interfield jitter is present when the scene is stopped.

• Journal of Broadcast Engineering
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• v.10 no.1 s.26
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• pp.77-82
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• 2005

We propose a highly Integrated motion estimation processor (MEP) for efficient video compression in an SoC platform. When compressing video by the standards like MPEG-4 and H.263, the macroblock related functions motion compensation. mode decision, motion vector prediction, and motion vector difference calculation require the frequent intervention of MCU. Thus the proposed MEP incorporates those functions with the motion estimation capability to reduce the number of interrupts to MCU, which can lead to a highly efficient SoC system. For low-power consumption, the proposed MEP can prevent the temporally static area from motion estimation or can skip the half-pel motion estimation for those macroblocks whose modes are decided as INTRA.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.3
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• pp.1684-1699
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• 2017

The deblocking filter (DF) reduces blocking artifacts in encoded video sequences, and thereby significantly improves the subjective and objective quality of videos. Statistics show that the DF accounts for 5-18% of the total decoding time in high-efficiency video coding. Therefore, speeding up the DF will improve codec performance, especially for the decoder. In view of the rapid development of multicore technology, we propose a parallel DF scheme based on a modified order of accessing the coding tree units (CTUs) by analyzing the data dependencies between adjacent CTUs. This enables the DF to run in parallel, providing accelerated performance and more flexibility in the degree of parallelism, as well as finer parallel granularity. We additionally solve the problems of variable privatization and thread synchronization in the parallelization of the DF. Finally, the DF module is parallelized based on the HM16.1 reference software using OpenMP technology. The acceleration performance is experimentally tested under various numbers of cores, and the results show that the proposed scheme is very effective at speeding up the DF.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.8
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• pp.2120-2130
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• 1998

This paper concerns a design of programmable MPEG decoder for video processing by object unit on network. The decoder can process video data effectively by a embedded controller with stack buffers for supporting OOP (Object-Oriented Programming). The controller offers extended instructions that process several data types including 32bit integer type. In addition to that, we have a vector processor, in this decoder that can execute advanced compensation and prediction by half pixel and SA(Shape Adaptive)-IDCT of MPEG-4. Absolutors and halfers in the vector processor make this architecture extensive to a encoder. We verified the decoder with $0.6\mu\textrm{m}$ 5-Volt CMOS COMPASS library.

• Journal of Information Display
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• v.2 no.2
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• pp.13-21
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• 2001

We propose a universal image processor for a-Si TFT LCD of UXGA class that can display the full screen on the LCD panel with low resolution of video sources such as NTSC, VGA, SVGA, XGA, and SXGA by using the proposed interpolation filter. In addition, we propose a real-time contrast controller for image improvement of multi-gray scale image. The operation of the proposed methods has been verified using Synopsys VHDL and computer simulation. Results show that the proposed methods might be suitable for a UXGA LCD controller for real-time image improvement.

• Journal of Broadcast Engineering
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• v.10 no.1 s.26
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• pp.83-102
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• 2005

The problem of video scheduling is analyzed in the framework of divisible load scheduling. A divisible load can be divided into any number of fractions (parts) and can be processed/computed independently on the processors in a distributed computing system/network, as there are no precedence relationships. In the video scheduling, a frame can be split into any number of fractions (tiles) and can be processed independently on the processors in the network, and then the results are collected to recompose the single processed frame. The divisible load arrives at one of the processors in the network (root processor) and the results of the computation are collected and stored in the same processor. In this problem communication delay plays an important role. Communication delay is the time to send/distribute the load fractions to other processors in the network. and the time to collect the results of computation from other processors by the root processors. The objective in this scheduling problem is that of obtaining the load fractions assigned to each processor in the network such that the processing time of the entire load is a minimum. We derive closed-form expression for the processing time by taking Into consideration the communication delay in the load distribution process and the communication delay In the result collection process. Using this closed-form expression, we also obtain the optimal number of processors that are required to solve this scheduling problem. This scheduling problem is formulated as a linear pro-gramming problem and its solution using neural network is also presented. Numerical examples are presented for ease of understanding.