• Proceedings of the Korea Information Processing Society Conference
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• 2011.04a
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• pp.46-49
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• 2011

This paper is to implement MoIP platform to send and receive video and audio at the same time by using high-performance Dual Core Processor. Even if Wall-Pad key component of a home network system is released by using embedded processors, it's lacking of performance in terms of multimedia processing and feature of video telephony through which video and voice are exchanged simultaneously. The main reason could be that embedded processors currently being used do not provide enough performance to support both MoIP call features and various home network features simultaneously. In order to solve these problems, Dual processor could be used, but in the other hands it brings another disadvantage of high cost. Therefore, this study is to solve the home automation features and video telephony features by using Dual Core Processor based on ARM 11 Processor and implement the MoIP Wall-Pad which can reduce the board design costs and component costs, and improve performance. The platform designed and implemented in this paper verified performance of MoIP to exchange the video and voice at the same time under the situation of Ethernet network.

• 제어로봇시스템학회:학술대회논문집
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• 1990.10b
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• pp.1032-1036
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• 1990

This paper describes a system which enables a real-time measurement of 2-D water flow field. One distinctive feature of our system is that velocity vectors of water flow are obtained from the movement of tracer particles at video rate. In order to enable a fast measurement a real time video processor and two Digital Signal Processor(TMS32OC25) are employed. The real-time video processor extracts contours of tracer particles in order to reduce the amount of image data to be processed. And two DSP(Digital Signal Processor) analyse the correlation of every tracer paticle in the consecutive two images to obtain the velocity distribution of water flow.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.52 no.2
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• pp.85-90
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• 2003

This paper has presented the efficient implementation of MPEG-4 simple profile video decoder, which is used as video compression standard in mobile video communication. We have used the ARM9 processor in implementing this MPEG-4 simple profile, which requires much processing power and low power implementation. At first we implemented with C-language under the PC environment with ADS(ARM Developer Suite) environment, and then we have tried to reduce a clock cycle for a power consumption optimization through conversion an assembly language for C-code partly. We have verified the processor is operated at 22.47MHz operation after optimization, but 148MHz before optimization.

• Journal of the Institute of Convergence Signal Processing
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• v.7 no.4
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• pp.207-213
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• 2006

This paper presents the design and implementation of a video processor for the device of need TV-OUT function. The designed video processor satisfies the standard conditions of ITU-R(International Telecommunication Union-Radiocommunication) BT.470. Also, in order to apply various digital device, we concentrate upon hardware complexity. ITU-R BT.470 can be classified as NTSC, PAL or SECAM. NTSC and PAL use QAM(Quardarature Amplitude Modulation) to transmit color difference signals and SECAM uses FM(Frequency Modulation). FM must have antic-cloche filter but filter recommended by ITU-R BT.470 is not easy to design due to sharpness of the frequency response. So this paper proposes that the special quality of anti-cloche filter is transformed easy to design and the modulation method is modified to be identical with the result required at standard. The processor can control power consumption by output mode to apply portable digital devices. The proposed processor is experimentally demonstrated with ALTERA FPGA APEX20KE EP20K1000EBC652-3 device and SAMSUNG LCD-TV.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.8 no.10
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• pp.3520-3537
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• 2014

Video copy detection methods have emerged in recent years for a variety of applications. However, the lack of efficiency in the usual retrieval systems restricts their use. In this paper, we propose a parallel implementation strategy for content based video copy detection (CBCD) by using a multi-core processor. This strategy can support video copy detection effectively, and the processing time tends to decrease linearly as the number of processors increases. Experiments have shown that our approach is successful in speeding up computation and as well as in keeping the performance.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.3
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• pp.841-846
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• 2010

This paper presents design and implementation of an intelligent video surveillance system. The proposed system has advantages of management efficiency and operation robustness unrelated to working condition compared to conventional CCTV based system. The system hardware is designed and implemented by using commercial chips such as digital media processor and video encoder, video decoder and the functions of software are to analyze temperature distribution of a infrared image and to detect disaster situation such as fire. The required functions are confirmed by testing of the prototype and we verified practicality of the system.

• Journal of Broadcast Engineering
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• v.24 no.1
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• pp.182-185
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• 2019

This paper analyzes performances of modules in implementing a programmable multi-format video decoder. The goal of the proposed platform is the high-end Full High Definition (FHD) video decoder. The proposed multi-format video decoder consists of a reconfigurable processor, dedicated bit-stream co-processor, memory controller, cache for motion compensation, and flexible hardware accelerators. The experiments suggest performance baseline of modules for the proposed architecture operating at 300 MHz clock with capability of decoding HEVC bit-streams of FHD 30 frames per second.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.21 no.6
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• pp.161-169
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• 2011

Recent intelligent video surveillance system asks for development of more advanced technology for analysis and recognition of video data. Especially, machine learning algorithm such as Support Vector Machine (SVM) is used in order to recognize objects in video. Because SVM training demands massive amount of computation, parallel processing technique is necessary to reduce the execution time effectively. In this paper, we propose a parallel processing method of SVM training with a multi-core processor. The results of parallel SVM on a 4-core processor show that our proposed method can reduce the execution time of the sequential training by a factor of 2.5.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.58-65
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• 2011

This paper presents an ASIP (Application-specific Instruction Processor) for motion estimation that employs specific IME instructions and its programmable and reconfigurable hardware architecture for various video codecs, such as H.264/AVC, MPEG4, etc. With the proposed specific instructions and variable point 2D SAD hardware accelerator, it can handle the real-time processing requirement of High Definition (HD) video. With the SAD unit and its parallel operations using pattern information, the proposed IME instructions support not only full search algorithms but also other fast search algorithms. The hardware size is 25.5K gates for each Processing Element Group (PEG) which has 128 SAD Processor Elements (PEs). The proposed ASIP has been verified by the Synopsys Processor Designer and implemented by the Design Compiler using the IBM 90nm process technology. The hardware size is 453K gates for the IME unit and the operating frequency is 188MHz for 1080p@30 frame in real time. The proposed ASIP can reduce the hardware size about 26% and the number of operation cycles about 18%.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.298-300
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• 2004

In the decoding process of interframe wavelet coding, the inverse wavelet transform requires huge computational complexity. However, the decoder may need to be used in various devices such as PDAs, notebooks, PCs or set-top Boxes. Therefore, the decoder's complexity should be adapted to the processor's computational power. A decoder designed in accordance with the processor's computational power would provide optimal services for such devices. So, it is natural that the complexity scalability and the low complexity codec are also listed in the requirements for scalable video coding. In this contribution, we develop a method of controlling and lowering the complexity of the spatial wavelet transform while sustaining almost the same coding efficiency as the conventional spatial wavelet transform. In addition, the proposed method may alleviate the ringing effect for certain video data.