• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.1109-1112
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• 1999

본 논문에서는 영상확대 chip의 video 입력부에 부분화면을 저장할 frame memory의 구조를 개선하고자 하였다. 영상확대 video scaler인 gm833×2는 입력단 측에 frame buffer memory가 필요하게 되지만, 이를 외부에 장착하려면 일반적으로 대용량의 FIFO 메모리를 사용하게 된다. 이것은 dualport SRAM으로 구성이 되며, 메모리 제어를 고가의 FIFO칩에 의존하는 결과를 가져온다. 또한 기존의 scaler chip은 단순히 확대처리만을 하며, 입력 전, 후에 data의 변경 또는 이미지처리가 불가능한 구조가 된다. 본 논문에서는 외부에 필요한 메모리를 내장한 새로운 기능의 chip을 설계하는 데에 있어 필수적인 메모리제어 로직을 제안하고자 한다. 여기서는 더 나은 기능의 향상된 메모리 제어회로를 제시하고 이를 One-chip에 집적할 수 있도록 하였다 이를 사용한 Video Scaler Processor chip은 SDRAM을 별도의 제어회로 없이 외부에 장착할 수 있도록 하여 scaler의 기능을 향상시키면서 전체 시스템의 구조를 간단히 할 수 있을 것으로 기대된다. 본 논문에서는 먼저 메모리 제어회로를 포함한 Video Scaler Processor chip의 메모리제어 하드웨어의 구조를 제시하고, 메모리 access model과 제어로직을 소개하고자 한다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1895-1900
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• 2010

In this paper, we propose the hardware architecture of a display converter which is consisted of four functional blocks. The four functional blocks consists of a set of color space converter, de-interacer, video display scaler, and gamma corrector. After the proposed architecture was implemented into hardware, we verified that it operated exactly. The designed hardware has 7,629 LUT and 6,800 Logic Register in Stratix device of Altera and operates in 270 MHz clock frequency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.1
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• pp.80-87
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• 2006

SONY corporation preoccupies $80\%$ of a market of the CCD used in a CCTV system. The CCD of SONY have high duality which can not follow the progress of capability. But there are some problems which differ the clock frequency used in CCD from the frequency used in common video encoder. To get the result by using common video encoder, the system needs a scaler that could adjust image size and PLL that synchronizes CCD's with encoder's clock So, this paper proposes the video encoder that is activated at equal clock used in CCD without scaler and PLL. The encoder converts ITU-R BT.601 4:2:2 or ITU-R BT.656 inputs from various video sources into NTSC or PAL signals in CVBS. Due to variable clock, property of filters used in the encoder is automatically changed by clock and filters adopt multiplier-free structures to reduce hardware complexity. The hardware bit width of programmable digital filters for luminance and chrominance signals, along with other operating blocks, are carefully determined to produce hish-quality digital video signals of ${\pm}1$ LSB error or less. The proposed encoder is experimentally demonstrated by using the Altera Stratix EP1S80B953C6ES device.

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.3
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• pp.93-101
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• 2001

In this paper, we propose an image downscaler used in multimedia video applications, such as DTV, TV-PIP, PC-video, camcorder, videophone and so on. The proposed image downscaler provides a scaled image of high-quality and high-performance. This paper will explain the scaling theory using two-dimensional digital filters. It is the method that removes an aliasing noise and decreases the hardware complexity, compared with Pixel-drop and Upsamling. Also, this paper will prove it improves scaling precisians and decreases the loss of data, compared with the Scaler32, the Bt829 of Brooktree, and the SAA7114H of Philips. The proposed downscaler consists of the following four blocks: line memory, vertical scaler, horizontal scaler, and FIFO memory. In order to reduce the hardware complexity, the using digital filters are implemented by the multiplexer-adder type scheme and their all the coefficients can be simply implemented by using shifters and adders. It also decreases the loss of high frequency data because it provides the wider BW of 6MHz as adding the compensation filter. The proposed downscaler is modeled by using the Verilog-HDL and the model is verified by using the Cadence simulator. After the verification is done, the model is synthesized into gates by using the Synopsys. The synthesized downscaler is Placed and routed by the Mentor with the IDEC-C632 0.65${\mu}{\textrm}{m}$ library for further IC implementation. The IC master is fixed in size by 4,500${\mu}{\textrm}{m}$$\times$4,500${\mu}{\textrm}{m}$. The active layout size of the proposed downscaler is 2,528${\mu}{\textrm}{m}$$\times$3,237${\mu}{\textrm}{m}$.

• Journal of IKEEE
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• v.28 no.1
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• pp.26-32
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• 2024

Recently, various video resolution formats have emerged, and digital devices have built in dedicated scaler chips to support them by enlarging or reducing the resolution of input videos. Therefore, the performance and hardware size of scaler chips are important. In this paper, the combinatorial interpolation scaler algorithm proposed by Han is used to design the hardware using the line memory structure with dual-clock proposed by Han and Jung. The proposed hardware is capable of real-time processing in QHD environments, designed using Verilog, and validated using Xilinx's Vivado 2023.1. We also verify the performance of Han's proposed algorithm with a quantitative numerical evaluation of the proposed hardware.

• Proceedings of the Korean Society of Computer Information Conference
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• 2015.07a
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• pp.196-197
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• 2015

본 논문에서는 산업용 컴퓨터에서 사용할 마우스와 터치스크린을 이용한 산업용 컴퓨터 인터페이스 장치 구현에 대하여 연구하였다. 산업용 제어 현장에서 사용되는 제어용 컴퓨터의 입출력 장치는 확장성을 고려하여 설계되지 않았기 때문에 현재의 컴퓨터 주변장치를 직접 사용할 수 없는 경우가 대부분이다. 본 논문에서는 산업용컴퓨터에서 사용되는 라이트펜과 모니터를 현재 주로 사용하는 마우스와 LCD모니터로 입출력이 가능하도록 하는 인터페이스 장치를 개발하여, 생산 공정에서 사용하는 산업용 컴퓨터의 활용도를 높이고자 한다. 산업용 컴퓨터 인터페이스장치는 ARM 기반 MPU를 이용하여 영상 신호와 외부 입력장치의 자료를 처리하고, CPLD에서 생성된 신호를 제어용 컴퓨터로 입력하였다. 제어컴퓨터의 영상신호를 다양한 모니터와 인터페이스 할 수 있도록 비디오 스케일러(Video Scaler)를 사용하였다. 구현한 인터페이스 장치는 다양한 장치들을 산업용컴퓨터에서 사용이 가능함을 보였다.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.5
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• pp.575-582
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• 2014

One of the most important decision making is which product's components should make in-house and which should they outsource. This paper suggests a framework to solve above question. This paper applies to LCD TV industry with AHP analysis. The results shows that Scaler chip, LCD panel, MPEG decoder, and Video decoder are important components. Samsung Electronics turn out make in-house these core component. This research will be a good guideline for selecting core component.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.2
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• pp.790-809
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• 2019

The design of an efficient scaler to enhance the edge data is one of the most important issues in video signal applications, because the perceptual quality of the processed image is sensitively affected by the degradation of edge data. Various conventional scaling schemes have been proposed to enhance the edge data. In this paper, we propose an efficient scaling algorithm for this purpose. The proposed method is based on the discrete cosine transform-based interpolation filter (DCT-IF) because it outperforms other scaling algorithms in various configurations. The proposed DCT-IF incorporates weighting parameters that are optimized for training data. Simulation results show that the quality of the resized image produced by the proposed DCT-IF is much higher than that of those produced by the conventional schemes, although the proposed DCT-IF is more complex than other conventional scaling algorithms.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2015.07a
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• pp.173-176
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• 2015

최근 고화질 영상의 수요가 증가함에 따라, UHD급 디스플레이의 디지털 기기가 등장하기 시작했다. 하지만 기존의 스케일러 모듈에 사용된 보간법들로는 기존의 저해상도의 영상 콘텐츠로부터 고품질의 영상을 획득하기가 어렵다. 따라서 본 논문에서는 고품질의 영상을 획득 가능한 초고해상도 영상에 적합한 스케일러를 제안한다.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.748-751
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• 1997

The White Beamline of the Pohang Accelerator Laboratory(PAL) consists of main and second slits, a microprobe system, two ion chambers, a video-microscope, and a Si(Li) detector. These machine components must be controlled remotely through computer system to make user experiments precise and speedy. A real-time computer control system was developed to control and monitor these machine components. A VNIEbus computer with OS-9 real-time operating system was used for low-level data acquisition and control. VME I/O modules were used for step motor control and scaler control. The software has modular structure for maximum performance and easy maintenance. We developed database, I/O driver, and control software. We used PC/Window95 for data logging and operator interface. Visual C++ was used graphical user interface programming. RS232C was used for communication between VME and PC.