• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.99-102
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• 2000

Via for achieving reliable fabrication of MCM-D substrate was formed on the photosensitive BCB layer. MCM-D substrate consists of photosensitive BCB(Benzocyclobutene) interlayer dielectric and copper conductors. In order to form the vias in photosensitive BCB layer, the process of BCB and plasme etch using $C_2$F$_{6}$ gas were evaluated. The thickness of BCB after soft bake was shrunk down to 60% of the original. AES analysis was done on two vias, one is etched in $C_2$F$_{6}$ gas and the other is non etched. On via etched in $C_2$F$_{6}$, native C was detected and the amount of native C was reduced after Ar sputter. On via non etched in $C_2$F$_{6}$, organic C was detected and amount of organic C was reduced a little after Ar sputter. As a result of AES, BCB residue was not removed by Ar sputter, so plasma etch is necessary for achieving reliable via.ble via.

• Journal of Sensor Science and Technology
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• v.28 no.2
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• pp.127-132
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• 2019

In this study, the fabrication of through-silicon vias (TSVs) filled with SWNTs/Sn by utilizing surface/bulk micromachining and MEMS technologies is proposed. Tin (Sn) and single-walled nanotube (SWNT) powders are used as TSV interconnector materials in the development of a novel TSV at low temperature. The measured resistance of a TSV filled with SWNT/Sn powder is considerably reduced by increasing the fraction of Sn and is lower than that of a TSV filled with only Sn. This is because of a decrease in the surface scattering of electrons along with an increase in the grain size of sintered SWNTs/Sn. The proposed method is conducted at low temperatures (< $400^{\circ}C$) due to the low melting temperature of Sn; hence, the proposed TSVs filled with SWNTs/Sn can be utilized in CMOS based applications.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.261-278
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• 2003

Concepts.Wafer-Level Chip-Scale Concept with Handling Substrate.Low Accuracy Placement Layout with Isolation Trench.Possible Pitch of Interconnections down to $10{\mu}{\textrm}{m}$ (Sn-Grains).Wafer-to-Wafer Equipment Adjustment Accuracy meets this Request of Alignment Accuracy (+/-1.5 ${\mu}{\textrm}{m}$).Adjustment Accuracy of High-Speed Chip-to-Wafer Placement Equipment starts to meet this request.Face-to-Face Modular / SLID with Flipped Device Orientation.interchip Via / SLID with Non-Flipped Orientation SLID Technology Features.Demonstration with Copper / Tin-Alloy (SLID) and W-InterChip Vias (ICV).Combination of reliable processes for advanced concept - Filling of vias with W as standard wafer process sequence.No plug filling on stack level necessary.Simultanious formation of electrical and mechanical connection.No need for underfiller: large area contacts replace underfiller.Cu / Sn SLID layers $\leq$ $10{\mu}{\textrm}{m}$ in total are possible Electrical Results.Measurements of Three Layer Stacks on Daisy Chains with 240 Elements.2.5 Ohms per Chain Element.Contribution of Soldering Metal only in the Range of Milliohms.Soldering Contact Resistance ($0.43\Omega$) dominated by Contact Resistance of Barrier and Seed Layer.Tungsten Pin Contribution in the Range of 1 Ohm

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1001-1004
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• 1998

In this paper, we present a gridless router for MCMs. Instead of the commonly employed grid a set of comer stitched tiles are used as a routing framework. The router routes variablewidth pins with wires of any width. It also a allows arbitrary location of terminals, wires, and vias. It performs faster than most grid-based MCM routers and produces the routing results which are comparable to their achievements.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.341-344
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• 2000

Several new via structures in printed circuit boards are proposed, fabricated and characterized in RF regime. The new structure with a larger inductance component in the bottom layer shows 3㏈ improvement over the conventional structure. The ADS simulation with model parameters extracted from 3D fie]d solver matches with the characterization of these vias

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.05a
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• pp.69-73
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• 2002

In ceramic systems, many components including embedded passives and TRL(transmission line) are used for composition of 3-dimensional circuit. So the exact analysis on this components, As for the TRL's, material properties including electrical conductivity of metal, loss factor and effective dielectric constant of dielectric material and geometrical factors like roughness of surface, vias, dimension of stripline structure have a large effect on the charactersistics of transmission lines. In this research, of effect of material and geometrical factors on the characteristics of stripline structure is analyzed and quantified by simulation and measurement.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2007.11a
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• pp.57-58
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• 2007

본 연구에서는 실리콘 식각 공정 중 하나인 BOSCH 공정 이후 문제가 되는 scallops를 후처리 공정인 RCA 클리닝 공정, KOH와 IPA를 이용한 습식식각 공정을 이용하여 제거하는 방법을 개발하였다. 또한 Via-Hole 에칭 공정이후 전기적 절연을 위해 측벽에 증착된 TEOS 표면에 대하여 분석하였다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.9 s.112
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• pp.883-889
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• 2006

In this paper, parasitic resonance modes generated in a conductor backed coplanar wave guide(CBCPW) and stripline band pass filter(BPF) and the oscillation phenomena of a 40 GHz power amplifier module(PAM) are analyzed and several methods to suppress them are presented for low-temperature co-fired ceramic(LTCC) based millimeter-wave RF System-in-Package(SiP) applications. Parasitic rectangular wave guide(RWG) modes of the CBCPW structure are completely suppressed in the operation frequency band by decreasing the distance between its vias and by increasing the mode frequency. In the stripline structure, RWG resonance modes are clearly eliminated by removing some vias facing each other and by placing them diagonally. In the case of the 40 GHz PAM, in order to reduce a cross talk due to radiation that is generated from interconnection discontinuities, high isolation structures such as embedded DC bas lines and CPW signal lines are used and then the oscillated PAM is improved.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.5
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• pp.508-514
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• 2013

Substrate integrated waveguide(SIW) constructed by two metal planes and conductive vias in a dielectric substrate, have all the conductors connected each other and hence, cannot be biased by DC sources. We propose a new folded corrugated substrate integrated waveguide(FCSIW) that can be DC-biased. Since the proposed FCSIW replaces the SIW conducting vias by folded open subs, it can supply the DC sources. The FCSIW has better transmission characteristics and 30 % less width than the common corrugated substrate integrated waveguide(CSIW) having a serious leakage generation problem. The FCSIW shows better insertion loss(1.49 dB) compared with that(3.08 dB) of the CSIW measured for 154 mm length devices and averaged at 9~15 GHz frequency band. No leakage has been observed from crosstalk measurements of the FCSIW.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.366-369
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• 2003

The vertical fountain plating system with the point contact has been used in semiconductor industry. But the plating shape in the opening of photoresist becomes gradated shape, because bubbles from the wafer surface are difficult to escape from the deep openings, vias. So, we designed the tilted electrode ring contact to get uniform bump height on all over the wafer and evaluated the film uniformity by SEM and $\alpha$-step. A photoresist was coated to a thickness of $60{\mu}m$ and vias were patterned by a contact aligner After via opening, solder layer was electroplated using the fountain plating system and the tilted electrode ring contact system. In $\alpha$-step measurement, film uniformities in the fountain plating system and the tilted electrode ring contact system were ${\pm}16%,\;{\pm}3.7%$ respectively. In this study, we could get high uniformity bumps by the tilted electrode ring contact system. So, tilted electrode ring contact system is expected to improve workability and yield in module process.