• 반도체디스플레이기술학회지
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• 제3권3호
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• pp.5-9
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• 2004

A new wafer level packaging scheme is presented as an alternative to MEMS package. The proof-of-concept structure is fabricated and evaluated to confirm the feasibility of the idea for MEMS wafer level packaging. The scheme of this work is developed using an electroplated tin (Sn) solder. The critical difference over conventional ones is that wafers are laterally bonded by solder reflow after LEGO-like assembly. This lateral bonding scheme has merits basically in morphological insensitivity and its better bonding strength over conventional ones and also enables not only the hermetic sealing but also its electrical interconnection solving an open-circuit problem by notching through via-hole. The bonding strength of the lateral bonding is over 30 Mpa as evaluated under shear and the hermeticity of the encapsulation is 2.0$\times10^{-9}$mbar.$l$/sec as examined by pressurized Helium leak rate. Results show that the new scheme is feasible and could be an alternative method for high yield wafer level packaging.

• 전기화학회지
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• 제2권4호
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• pp.237-241
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• 1999

펄스전착법에 의한 구리박막의 특성과 via hole 충진 특성을 연구하였다. 특히 구리박막의 특성에 미치는 첨가제의 영향을 중점적으로 다루었다. 펄스 전류와 첨가제를 사용하여 전착한 구리박막은 83.4 MPa이하의 낮은 인장응력을 가졌으며 높은 Cu (111) 우선 배향성을 나타냈다. Superfilling에 의해 최고 $0.25{\mu}m, 6: 1$ 정도의 고 종횡비를 가지는 via hole에 결함 없이 성공적으로 충진할 수 있었으며 미세 구조를 관찰한 결과 쌍정에 의한 변형이 일어났음을 알 수 있었다. $500^{\circ}C$에서 1시간 동안 진공열처리를 했을 경우 두께의 $1\~2$배에 달하는 결정립을 가지는 bamboo구조를 나타냈으며 이때 전기비저항은 $1.8\~2.0{\mu}{\Omega}{\cdot}cm$을 나타냈다.

• 마이크로전자및패키징학회지
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• 제22권4호
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• pp.47-56
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• 2015

본 논문에서는 HDI(High Density Interconnection) 기판의 코어로 사용될 수 있는 카본 CCL(Copper Claded Layer)의 열거동 및 신뢰성 특성을 실험과 CAE를 이용한 수치해석을 통해 평가하였다. 카본 CCL의 특성평가를 위해 기존 FR-4 코어와 heavy cu 코어와 비교하였다. 연구결과에 의하면 pitch계열 카본코어가 적용된 PCB의 휨강도가 가장 높고 온도에 따른 변형량이 가장 낮았다. 또한, HDI 신뢰성평가 기준의 TC(Thermal Cycling), LLTS(Liquid-to-Liquid Thermal Shock), Humidity 실험을 통해 카본코어가 적용된 PCB는 신뢰성이 확보되었음을 확인하였다. 카본 파이버에 의한 불균일한 비아홀의 표면형상 여부와 드릴비트 마모 가능성을 분석하였는데 비아홀의 표면은 균일하고, 드릴비트의 표면도 매끄러워 카본 CCL의 우수한 드릴가공성도 확인하였다.

• 대한용접접합학회:학술대회논문집
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• 대한용접접합학회 2007년 추계학술발표대회 개요집
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• pp.229-231
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• 2007

Recently, 3D-electronic packaging by TSV is in interest. TSV(Through Silicon Via) is a interconnection hole on Si-wafer filled with conducting metal such as Copper. In this research, chips with TSV are connected by electroplated Sn bump without PR. Then chips with TSV are put together and stacked by the methode of Reflow soldering. The stacking was successfully done and had no noticeable defects. By eliminating PR process, entire process can be reduced and makes it easier to apply on commercial production.

• 마이크로전자및패키징학회지
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• 제5권2호
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• pp.21-26
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• 1998

대용량, 고속데이터 처리가 요구되는 System 개발은 이들의 복잡하고 고기능의 회 로 구현이 가능하냐에 달려 있고 또한 이들고기능 요구를 가장 잘 만족할수 있는 패키지는 MCM 이라 할 수있다. 시스템의 고속화, 소형화는 회로의 복잡성을 요구하는 있는 이를 패 키지로 구현하는 MCM은 시험성 확보에 심각한 문제점으로 나타나고 있다. 본 논문에서는 고밀도 구조의 MCM 기판에 대한 Interconnetion Line 시험검증을 위한 Flying Prober의 적 용 및 모듈 패키징 공정에 대한 조립성 검증을 위한 BST에 대해 설명한다. 연구에 사용된 MCM 모듈은 MCM-D 공정으로 제작되었으며 31um 신호선폭, 50um Via Hole Dia. 5신호 선층 5절연층 및 455 Net의 기판으로절연층은 Dow chemical의 BCB-4024/4026을 적용하였 다. 조립은 3 ASIC, 24소자 실장 및 2000 Wire Bonding으로 이루어지며 패키지는 방열특성 을 고려한 BGA(491 I /O,50mil pitch)를 개발하여 사용하였다. MCM 기판의미세패턴으로 구성된 Interconnection Line에 대해 Fine Ptich Probing이 가능한 Flying Prober를 사용하 여 평가하였으며 BST를 이용하여 실장소자의 KGD평가 및 능동, 수동소자가 실장된 MCM Package의 조립시험성을 확보할수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권3호
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• pp.133-139
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• 2007

Future MEMS systems will be composed of larger varieties of devices with very different functionality such as electronics, mechanics, optics and bio-chemistry. Integration technology of heterogeneous devices must be developed. This article first deals with the current development trend of new fabrication technologies; those include self-assembling of parts over a large area, wafer-scale encapsulation by wafer-bonding, nano imprinting, and roll-to-roll printing. In the latter half of the article, the concept towards the heterogeneous integration of devices and functionality into micro/nano systems is described. The key idea is to combine the conventional top-down technologies and the novel bottom-up technologies for building nano systems. A simple example is the carbon nano tube interconnection that is grown in the via-hole of a VLSI chip. In the laboratory level, the position-specific self-assembly of nano parts on a DNA template was demonstrated through hybridization of probe DNA segments attached to the parts. Also, bio molecular motors were incorporated in a micro fluidic system and utilized as a nano actuator for transporting objects in the channel.

• 센서학회지
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• 제29권5호
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• pp.354-359
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• 2020

The high vacuum hermetic sealing technique ensures excellent performance of MEMS resonators. For the high vacuum hermetic sealing, the customization of anodic bonding equipment was conducted for the glass/Si/glass triple-stack anodic bonding process. Figure 1 presents the schematic of the MEMS resonator with triple-stack high-vacuum anodic bonding. The anodic bonding process for vacuum sealing was performed with the chamber pressure lower than 5 × 10^-6 mbar, the piston pressure of 5 kN, and the applied voltage was 1 kV. The process temperature during anodic bonding was 400 ℃. To maintain the vacuum condition of the glass cavity, a getter material, such as a titanium thin film, was deposited. The getter materials was active at the 400 ℃ during the anodic bonding process. To read out the electrical signals from the Si resonator, a vertical feed-through was applied by using through glass via (TGV) which is formed by sandblasting technique of cap glass wafer. The aluminum electrodes was conformally deposited on the via-hole structure of cap glass. The TGV process provides reliable electrical interconnection between Si resonator and aluminum electrodes on the cap glass without leakage or electrical disconnection through the TGV. The fabricated MEMS resonator with proposed vacuum packaging using three-layer anodic bonding process has resonance frequency and quality factor of about 16 kHz and more than 40,000, respectively.