• Journal of Sensor Science and Technology
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• v.24 no.1
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• pp.10-14
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• 2015

This paper reports the results of a study on the optimization of the etching profile, which is an important factor in deep-reactive-ion etching (DRIE), i.e., dry etching. Dry etching is the key processing step necessary for the development of the Internet of Things (IoT) and various microelectromechanical sensors (MEMS). Large-area etching (open area > 20%) under a high-frequency (HF) condition with nonoptimized processing parameters results in damage to the etched sidewall. Therefore, in this study, optimization was performed under a low-frequency (LF) condition. The HF method, which is typically used for through-silicon via (TSV) technology, applies a high etch rate and cannot be easily adapted to processes sensitive to sidewall damage. The optimal etching profile was determined by controlling various parameters for the DRIE of a large Si wafer area (open area > 20%). The optimal processing condition was derived after establishing the correlations of etch rate, uniformity, and sidewall damage on a 6-in Si wafer to the parameters of coil power, run pressure, platen power for passivation etching, and $SF_6$ gas flow rate. The processing-parameter-dependent results of the experiments performed for optimization of the etching profile in terms of etch rate, uniformity, and sidewall damage in the case of large Si area etching can be summarized as follows. When LF is applied, the platen power, coil power, and $SF_6$ should be low, whereas the run pressure has little effect on the etching performance. Under the optimal LF condition of 380 Hz, the platen power, coil power, and $SF_6$ were set at 115W, 3500W, and 700 sccm, respectively. In addition, the aforementioned standard recipe was applied as follows: run pressure of 4 Pa, $C_4F_8$ content of 400 sccm, and a gas exchange interval of $SF_6/C_4F_8=2s/3s$.

• Journal of the Microelectronics and Packaging Society
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• v.7 no.4
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• pp.23-29
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• 2000

We demonstrate the fabrication method of high-density and high-quality solder bump solving a copper (Cu) cross-contamination in Si-LSI laboratory. The Cu cross-contamination is solved by separating solder-bump process by two steps. Former is via-formation process excluding Cu/Ti under ball metallurgy (UBM) layer sputtering in Si-LSI laboratory. Latter is electroplating process including Ti-adhesion and Cu-seed layers sputtering out of Si-LSI laboratory. Thick photoresist (PR) is achieved by a multiple coating method. After TiW/Al-electrode sputtering for electroplating and via formation in Si-LSI laboratory, Cu/Ti UBM layer is sputtered on sample. The Cu-seed layer on the PR is etched during Cu-electroplating with low-electroplating rate due to a difference in resistance of UBM layer between via bottom and PR. Therefore Cu-buffer layer can be electroplated selectively at the via bottom. After etching the Ti-adhesion layer on the PR, Sn/Pb solder layer with a composition of 60/40 is electroplated using a tin-lead electroplating bath with a metal stoichiometry of 60/40 (weight percent ratio). Scanning electron microscope image shows that the fabricated solder bump is high-uniformity and high-quality as well as symmetric mushroom shape. The solder bumps with even 40/60 $\mu\textrm{m}$ in diameter/pitch do not touch during electroplating and reflow procedures. The solder-bump process of high-uniformity and high-density with the Cu cross-contamination free in Si-LSI laboratory will be effective for electronic microwave application.

• Journal of the Korean Vacuum Society
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• v.15 no.4
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• pp.387-394
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• 2006

In this study, the effect of using a neutral beam formed by low-angle forward reflection of a reactive ion beam on aspect-ratio-dependent etching (ARDE) has been investigated. When a SF6 Inductively Coupled Plasma and $SF_6$ ion beam etching are used to etch poly-Si, ARDE is observed and the etching of poly-Si on $SiO_2$ shows a higher ARDE effect than the etching of poly-Si on Si. However, by using neutral beam etching with neutral beam directionality higher than 70 %, ARDE during poly-Si etching by $SF_6$ can be effectively removed, regardless of the sample conditions. The mechanism for the removal of ARDE via a directional neutral beam has been demonstrated through a computer simulation of different nanoscale features by using the two-dimensional XOOPIC code and the TRIM code.

• Proceedings of the Materials Research Society of Korea Conference
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• 1998.11a
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• pp.117-117
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• 1998

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.10a
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• pp.160-163
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• 2002

Micro via hole Fabrication is studied by means of minimizing method to circuit size as many electric products developed to portable and minimize. Most of currently micro via hole fabrication using laser is that fabricate insulator layer using CO2 Laser after Cu layer by etching, or fabricate insulator layer using IR after trepanning Cu by UV. In this paper, it was performed that a metal layer and insulator layer were worked upon only one UV laser, and increase to processing speed by experiment.

• ETRI Journal
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• v.26 no.4
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• pp.297-306
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• 2004

A plasma is a collection of charged particles and on average is electrically neutral. In fabricating integrated circuits, plasma etching is a key means to transfer a photoresist pattern into an underlayer material. To construct a predictive model of plasma-etching processes, a polynomial neural network (PNN) is applied. This process was characterized by a full factorial experiment, and two attributes modeled are its etch rate and DC bias. According to the number of input variables and type of polynomials to each node, the prediction performance of the PNN was optimized. The various performances of the PNN in diverse environments were compared to three types of statistical regression models and the adaptive network fuzzy inference system (ANFIS). As the demonstrated high-prediction ability in the simulation results shows, the PNN is efficient and much more accurate from the point of view of approximation and prediction abilities.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.27 no.3
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• pp.143-147
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• 2017

To evaluate surface characteristics and improve crystalline quality of AlN single crystal grown by physical vapor transport (PVT) method, wet chemical etching process using $KOH/H_2O_2$ mixture in a low temperature condition and thermal annealing process was proceeded respectively. Conventional etching process using strong base etchant at a high temperature (above $300^{\circ}C$) had formed over etching phenomenon according to crystalline quality of materials. When it occurred to over etching phenomenon, it had a low reliability of dislocation density because it cannot show correct number of etch pits per estimated area. Therefore, it was proceeded to etching process in a low temperature (below $100^{\circ}C$) using $H_2O_2$ as an oxidizer in KOH aqueous solution and to be determined optimum etching condition and dislocation density via scanning electron microscope (SEM). For improving crystalline quality of AlN single crystal, thermal annealing process was proceeded. When compared with specimens as-prepared and as-annealed, full width at half maximum (FWHM) of the specimen as-annealed was decreased exponentially, and we analyzed the mechanism of this process via double crystal X-ray diffraction (DC-XRD).

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.217-221
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• 2004

[ $CO_2$ ]laser ablation rates for bulk 4H-SiC substrates and GaN/AIN/SiC templates in the range 229-870 ${\mu}m.min^{-1}$ were obtained for pulse energies of 7.5-30 mJ over diameters of 50·500 ${\mu}m$ with a Q-switched pulse width of ${\sim}30$ nsec and a pulse frequency of 8 Hz. The laser drilling produces much higher etch rates than conventional dry plasma etching (0.2 - 1.3 ${\mu}m/min$) making this an attractive maskless option for creating through-wafer via holes in SiC or GaN/AlN/SiC templates for power metal-semiconductor field effect transistor applications. The via entry can be tapered to facilitate subsequent metallization by control of the laser power and the total residual surface contamination can be minimized in a similar fashion and with a high gas throughput to avoid redeposition. The sidewall roughness is also comparable or better than conventional via holes created by plasma etching.

• Journal of Korean society of Dental Hygiene
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• v.1 no.2
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• pp.251-260
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• 2001

The purpose of this article was to compare the fluoridation effect via individual tray with other professional methods. In oder to compare the fluoridation effect, 40 extracted human teeth was divided into 4 groups(each group was composed of 10 teeth) and the surface hardness of each group was tested in untreated, after fluoridation, after fluoridation and etching by 10% lactic acids. group I: no fluoridation(control) group II : fluoridation with 123%APF group III : fluoridation by iontophoresis with 2% NaF group IV : fluoridation by individual tray with 4% SnF2 gel Surface hardness was measured with Micro hardness tester(Shimadzu Co. Japan), Data analysis was conducted using the repeated measures ANOVA test. The results were as follows: 1. Four tested groups demonstrated nearly the same SMH in extracted state. 2. The SMH after fluoridation showed $330.57{\pm}139.09kg/mm^2$ in group IV, $221.79{\pm}187.48kg/mm^2$ in group II, $186.43{\pm}53.13kg/mm^2$ in group III. So the SMH of group IV, II were was significantly increased(p<0.01). 3. The SMH of group II, III, IV after acid etching was higher than the control group(p<0.01). 4. The SMH between group II, III, and IV after acid etching was not different significantly.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.3
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• pp.79-84
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• 2010

Formation of TSV (Through-Si-Via) with an Au seed layer and Cu filling to the via, simplification of bumping process for three dimensional stacking of Si dice were investigated. In order to produce the via holes, the Si wafer was etched by a DRIE (Deep Reactive Ion Etching) process using $SF_6$ and $C_4F_8$ plasmas alternately. The vias were 40 ${\mu}m$ in diameter, 80 ${\mu}m$ in depth, and were produced by etching for 1.92 ks. On the via side wall, a dielectric layer of $SiO_2$ was formed by thermal oxidation, and an adhesion layer of Ti, and a seed layer of Au were applied by sputtering. Electroplating with pulsed DC was applied to fill the via holes with Cu. The plating condition was at a forward pulse current density of 1000 mA/$dm^2$ for 5 s and a reverse pulse current density of 190 mA/$dm^2$ for 25 s. By using these parameters, sound Cu filling was obtained in the vias with a total plating time of 57.6 ks. Sn bumping was performed on the Cu plugs without lithography process. The bumps were produced on the Si die successfully by the simplified process without serious defect.