• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.1
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• pp.24-29
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• 2000

We propose a simple method to control the crystallization depth of amorphous silicon (a-Si) deposited by PECVD or LPCVD during the excimer laser annealing (ELA). Employing the new method, we have formed poly-Si/a-Si double film and fabricated a new poly-Si TFT with vertical a-Si offsets between the poly-Si channel and the source/drain of TFT without any additional photo-lithography process. The maximum leakage current of the new poly-Si TFT decreased about 80% due to the highly resistive vertical a-Si offsets which reduce the peak electric field in drain depletion region and suppress electron-hole pair generation. In ON state, current flows spreading down through broad a-Si cross-section in the vertical a-Si offsets and the current density in the drain depletion region where large electric field is applied is reduced. The stability of poly-Si TFT has been improved noticeably by suppressing trap state generation in drain region which is caused by high current density and large electric field. For example, ON current of the new TFT decreased only 7% at a stress condition where ON current of conventional TFT decreased 89%.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.48-52
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• 2014

In this paper, scaling down characteristics of vertical channel phase random access memory are investigated with device simulator and finite element analysis simulator. Electrical properties of select transistor are obtained by device simulator and those of phase change material are obtained by finite element analysis simulator. From the fusion of both data, scaling properties of vertical channel phase change random access memory (VPCRAM) are considered with ITRS roadmap. Simulation of set reset current are carried out to analyze the feasibility of scaling down and compared with values in ITRS roadmap. Simulation results show that width and length ratio of the phase change material (PCM) is key parameter of scaling down in VPCRAM. Thermal simulation results provide the design guideline of VPCRAM. Optimization of phase change material in VPCRAM can be achieved by oxide sidewall process optimization.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.196-197
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• 2006

In this paper, two types of vertical SIT(Static Induction Transistor) structures are proposed to improve their electrical characteristics including the blocking voltage. Besides, the two dimensional numerical simulations were carried out using ISE-TCAD to verify the validity of the device and examine the electrical characteristics. First, a trench gate region oxide power SIT device is proposed to improve forward blocking characteristics. Second, a trench gate-source region power SIT device is proposed to obtain more higher forward blocking voltage and forward blocking characteristics at the same size. The two proposed devices have superior electrical characteristics when compared to conventional device. In the proposed trench gate oxide power SIT, the forward blocking voltage is considerably improved by using the vertical trench oxide and the forward blocking voltage is 1.5 times better than that of the conventional vertical power SIT. In the proposed trench gate-source oxide power SIT, it has considerable improvement in forward blocking characteristics which shows 1500V forward blocking voltage at -10V of the gate voltage. Consequently, the proposed trench oxide power SIT has the superior stability and electrical characteristics than the conventional power SIT.

• Transactions on Electrical and Electronic Materials
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• v.13 no.2
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• pp.73-77
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• 2012

Operation of liquid crystal displays (LCDs) can be improved by monolithic integration of the pixel transistors with light emitting diodes (LEDs) on a single substrate. Conventional LCDs make use of filters to control the backlighting which reduces the overall efficiency. These LCDs also utilize LEDs in series which impose failure and they require high voltage for operation with a power factor correction. The screen of small hand-held devices can operate from moderate brightness. Therefore, III-V nanowires that are grown along with transistors over Silicon substrates can be utilized. Control of nanowire LEDs with nanowire transistors will significantly lower the cost, increase the efficiency, improve the manufacturing yield and simplify the structure of the small displays that are used in portable devices. The steps to grow nanowires on Silicon substrates are described. The vertical n-type and p-type nanowire transistors with surrounding gate structures are characterized. While biased at 0.5 V, nanowire transistors with minimum radius or channel width have an OFF current which is less than 1pA, an ON current more than 1 ${\mu}A$, a total delay less than 10 ps and a transconductance gain of more than 10 ${\mu}A/V$. The low power and fast switching characteristics of the nanowire transistor make them an ideal choice for the realization of future displays of portable devices with long battery lifetime.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.11
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• pp.1286-1293
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• 1988

A general closed form expression for the channel length of the self-aligned double-diffused MOS transistor is obtained from the 2-dimensional Gaussian doping profile. The proposed model in this paper is composed of the doping concentration of the substrate, the final surface doping concentration and the vertical junction depth of the each double-diffused region. The calculated channel length is in good agreement with the experimental results. Also, the optimum channel structure for the prevention of the channel puncthrough is obtained by the averaged doping concentration in the channel region. A correspondence between the results of device simulation of channel punchthrough and the estimations of simplified model is confirmed.

• Current Optics and Photonics
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• v.1 no.2
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• pp.157-162
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• 2017

In large liquid crystal displays, the image quality in an oblique viewing direction is a crucial issue. From this perspective, 8-domain polymer-stabilized vertical alignment (PS-VA) mode has been developed to suppress the color shift in oblique viewing directions, compared to that in 4-domain PS-VA mode. To realize the 8-domain PS-VA, the four domains in a pixel are each divided into two regions, such that applying different electric potentials result in different tilt angles in these two regions, while keeping four azimuthal directions in each domain. However, applying different voltages in a pixel causes drawbacks, such as requiring additional processes to construct a capacitor and a transistor, which will further reduce the aperture ratio. Here we propose a different approach to form the 8-domain, by controlling surface polar anchoring energy and the width of patterned electrodes in two regions of a pixel. As a result, the gamma-distortion index (GDI), measured at an azimuthal angle of $0^{\circ}$, is reduced by about 23% and 8%, compared to that of a conventional 4-domain at polar angles of $30^{\circ}$ and $60^{\circ}$ respectively.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.6
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• pp.124-130
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• 1989

For the higher density DRAM'S, innovations in fabrication process and circuit design which have led to dramatic density improvement are discussed from the desinger's perspective. A new dynamic RAM cell called Trench Epitaxial Transistor Cell(TETC) using trench technics and SEG have been developed for use in future megabit DRAMS. Storge electrode with $n^+$-polysilicon and $n^+$-source electrode are self-contacted in TETC. With keeping the storage capacitance large enough to prevent soft errors, the cell size reduced to 30% compare with existing BSE cell by utilizing the vertical capacitor made along the isolation region.

• Journal of IKEEE
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• v.22 no.3
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• pp.565-569
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• 2018

For the conventional power MOSFET (metal-oxide semiconductor field-effect transistor) device structure, there exists a tradeoff relationship between specific on-state resistance (Ron,sp) and breakdown voltage (BV). In order to overcome this tradeoff, a super-junction (SJ) trench MOSFET (TMOSFET) structure with uniform or non-uniform doping concentration, which decreases linearly in the vertical direction from the N drift region at the bottom to the channel at the top, for an optimal design is suggested in this paper. The on-state resistance of $0.96m{\Omega}-cm2$ at the SJ TMOSFET is much less than that at the conventional power MOSFET under the same breakdown voltage of 100V. A design methodology for the edge termination is proposed to achieve the same breakdown voltage and on-state resistance as the main body of the super-junction TMOSFET by using of the SILVACO TCAD 2D device simulator, Atlas.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2005.06a
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• pp.1011-1015
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• 2005

Fully digital controlled 20-bit magnet power supplies have been developed and successfully tested for closed orbit correction of PLS(Pohang Light Source). The new digital power supply has used fiber optics for 25kHz switching of IGBT drivers, and implemented DSP, ADC, Interlock, DCCT cards in a compact 3U-sized 19" chassis. Input/Output low-pass filters suppress harmonics of 60Hz line frequency and switching frequency noise effectively. Overall performance of the power supplies have been demonstrated as +/- 2ppm short-term stability(<1 min), and +/- 10ppm long-term stability(<36 hours). All the existing 12-bit 70 power supplies for vertical correction magnets will be replaced with new digital power supplies during 2005 summer shutdown period. In this paper, we will describe the hardware structure and control method of the digital power supply and the experimental results will be shown.

• Proceeding of EDISON Challenge
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• 2017.03a
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• pp.398-403
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• 2017

본 연구에서는 gate-all-around(GAA) 수직 나노선 Field-Effect Transistor(FET)의 소스/드레인 반도체/실리사이드 접합에 존재하는 Schottky 장벽이 트랜지스터의 DC특성에 미치는 영향에 대하여 조사하였다. Non-Equilibrium Green's Function와 Poisson 방정식 기반의 시뮬레이터를 사용하여, Schottky 장벽의 위치와 높이, 그리고 채널 단면적의 크기에 따른 전류-전압 특성 곡선과 에너지 밴드 다이어그램을 통해 분석을 수행하였다. 그 결과, 드레인 단의 Schottky 장벽은 드레인 전압에 의해 장벽의 높이가 낮아져 전류에 주는 영향이 작지만, 소스 단의 Schottky 장벽은 드레인 전압과 게이트 전압으로 제어가 불가능하여 외부에서 소스 단으로 들어오는 캐리어의 이동을 방해하여 큰 DC성능 저하를 일으킨다. 채널 단면적 크기에 따른 DC특성 분석 결과로는 동작상태의 전류밀도는 채널의 폭이 5 nm 일 때까지는 유지되고, 2 nm가 되면 그 크기가 매우 작아지지만, 채널 단면적은 Schottky 장벽에 영향을 끼치지 못하였다. 본 논문의 분석 결과로 향후 7 nm technology node 에 적용될 GAA 수직 나노선 FET의 소자 구조 설계에 도움이 되고자 한다.