DOI QR코드

DOI QR Code

Scaling Down Characteristics of Vertical Channel Phase Change Random Access Memory (VPCRAM)

  • Park, Chun Woong (Department of Electronic Engineering, Myongji University) ;
  • Park, Chongdae (Department of Electronic Engineering, Myongji University) ;
  • Choi, Woo Young (Department of Electronic Engineering, Myongji University) ;
  • Seo, Dongsun (Department of Electronic Engineering, Myongji University) ;
  • Jeong, Cherlhyun (Center for Theragnosis, Korea Institute of Science and Technology) ;
  • Cho, Il Hwan (Department of Electronic Engineering, Myongji University)
  • Received : 2013.08.25
  • Accepted : 2014.01.16
  • Published : 2014.02.28

Abstract

In this paper, scaling down characteristics of vertical channel phase random access memory are investigated with device simulator and finite element analysis simulator. Electrical properties of select transistor are obtained by device simulator and those of phase change material are obtained by finite element analysis simulator. From the fusion of both data, scaling properties of vertical channel phase change random access memory (VPCRAM) are considered with ITRS roadmap. Simulation of set reset current are carried out to analyze the feasibility of scaling down and compared with values in ITRS roadmap. Simulation results show that width and length ratio of the phase change material (PCM) is key parameter of scaling down in VPCRAM. Thermal simulation results provide the design guideline of VPCRAM. Optimization of phase change material in VPCRAM can be achieved by oxide sidewall process optimization.

Keywords

References

  1. Hangbing Lv, Yinyin Lin, Peng Zhou, Tingao Tang, Baowei Qiao, Yunfeng Lai, Jie Feng and Bomy Chen, "A nano-scale-sized 3D element for phase change memories," Semiconductor Science and Technology, vol. 21, p.1013, 2006 https://doi.org/10.1088/0268-1242/21/8/004
  2. B. C. Lee, P. Zhou, J. Yang, Y. Zhang, B. Zhao, E. Ipek, O. Mutlu, and D. burger, "Phase change technology and the future of main memory," IEEE Micro, vol. 30, p.143, 2010 https://doi.org/10.1109/MM.2010.24
  3. Kyung Soo Kim, JongHo Lee and Il Hwan cho : Highly Scalable Vertical Channel Phase Change Random Access Memory, Japanese Journal of Applied Physics, vol. 50, p.050206 , 2011 https://doi.org/10.7567/JJAP.50.050206
  4. Kyung Soo Kim and Il Hwan Cho, "Disturbance Characteristics of Vertical Channel Phase Change Random Access Memory Array," Japanese Journal of Applied Physics, vol. 51, p.084302, 2012 https://doi.org/10.7567/JJAP.51.084302
  5. Y. Matsui, K. Kurotsuchi, O. Tonomura, T. Morikawa, Y. Fujisaki, N. Matsuzaki, S. Hanzawa, M. Terao, N. Takaura, H. Moriya, T. Iwasaki, M. Moniwa, and T. Koga, "Ta_2O_5$ Interfacial Layer between GST and W Plug enabling Low Power Operation of Phase Change Memories," IEDM Tech. Dig., 2006, p. 1.
  6. Y. Sasago, M. Kinoshita, T. Morikawa, K. Kurotsuchi, S. Hanazawa, T. Mine, A. Shima, Y. Fujisaki, H. Kume, H. Moriya, N. Takaura, and K. Torii, "Cross-point phase change memory with 4F2 cell size driven by low-contact-resistivity poly-Si diode," Symp. VLSI Technology Dig. Tech., 2009, p. 24.
  7. Zhe Wu, Suyoun Lee, Young-Wook Park, Hyung- Woo Ahn, Doo Seok Jeong, Jeung-hyun Jeong, Kwangsoo No, and Byung-ki Cheong, "Improved stability of a phase change memory device using Ge-doped SbTe at varying ambient temperature," Applied Physics Letters, vol. 96, issue 13, p.133510, 2010 https://doi.org/10.1063/1.3374334
  8. 2012 ITRS roadmap

Cited by

  1. Resistive Switching Characteristics of Silicon Nitride-Based RRAM Depending on Top Electrode Metals vol.E98.C, pp.5, 2015, https://doi.org/10.1587/transele.E98.C.429
  2. A Dual-Data Line Read Scheme for High-Speed Low-Energy Resistive Nonvolatile Memories vol.26, pp.2, 2018, https://doi.org/10.1109/TVLSI.2017.2766150