• Journal of electromagnetic engineering and science
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• 제18권1호
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• pp.35-40
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• 2018

This study presents a vertical-type CMOS Hall device with improved sensitivity to detect a 3D magnetic field in various types of sensors or communication devices. To improve sensitivity, trenches are implanted next to the current input terminal, so that the Hall current becomes maximum. The effect of the dimension and location of trenches on sensitivity is simulated in the COMSOL simulator. A vertical-type Hall device with a width of $16{\mu}m$ and a height of $2{\mu}m$ is optimized for maximum sensitivity. The simulation result shows that it has a 23% better result than a conventional vertical-type CMOS Hall device without a trench.

• 마이크로전자및패키징학회지
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• 제9권4호
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• pp.25-29
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• 2002

기존 홀 센서의 단점을 개선하기 위해서 트랜치를 이용한 수직 홀 센서를 제작하였다. 수직 홀 센서는 센서의 칩 표면에 수평 자계를 검출할 수 있으며, 홀 센서는 실리콘 직접 본딩 기술에 의해 제작된 SOI 기판 위에 제작하였다. 기판 아래의 $SiO_2$층과 마이크로머시닝에 의한 트랜치가 홀 센서의 동작 영역을 정의한다. 홀 센서의 감도는 150V/AT로 측정되었으며 안정된 값을 나타내었다.

• 전자공학회논문지A
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• 제29A권3호
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• pp.72-78
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• 1992

The Silicon vertical Hall devices are fabricated using standard bipolar process and characterized in terms of the Hall voltage, sensitivities, and offset voltage. The Hall voltage and sensitivity of the devices showed good linearity with respect to the magnetic flux density and reverse supply voltage Vr. The sensitivity of device with P$^{+}$ isolation dam has been increased up to 1.2 times compared to that of device without the dam. With the condition of V$_{r}$=-5.0[V], B=0.4[T] and I$_{sup}$=1.0[mA], the Hall voltage and sensitivity of the device with P$^{+}$ isolation dam were about 29[mV] and 74[V/AT], respectively. These vertical Hall devices can be used as the adjustable magnetic fields sensor.

• 한국정보통신학회논문지
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• 제12권10호
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• pp.1890-1896
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• 2008

본 연구는 칩 표면에 수평 한 자기장을 검출하는 종형 Hall 소자를 바이폴라 기술로 제조하여 동작 및 잡음 특성을 조사하였다. P+ Isolation 댐을 설치한 소자(type B)가 설치하지 않는 소자(type A)보다 자기 감도는 약 1.2배 증가하였고, 역시 잡음도 증가하였다. 측정된 이 종형 Hall소자의 자기 검출 분해능은 f=1[KHz], 대역폭 1[Hz] 구동조건에서 type A는 약 $0.97[{\mu}T]$, type B는 $1.25[{\mu}T]$였다. 따라서 Hall 소자 구조 설계나 재료적인 면에서 볼 때, 낮은 잡음즉, 자기 검출분해능과 높은 감도 상관관계를 고려하여야 한다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 하계학술대회 논문집 C
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• pp.2023-2025
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• 2002

We have fabricated a novel vertical trench-Hall device sensitive to the magnetic field parallel to the sensor chip surface. The vertical trench-Hall device is built on SOI wafer which is produced by silicon direct bonding technology using bulk micromachining, where buried $SiO_2$ layer and surround trench define active device volume. Sensitivity up to 350 V/AT is measured.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 추계학술대회 논문집 전기물성,응용부문
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• pp.251-253
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• 2002

We have fabricated a novel Vertical Trench Hall-Effect Device sensitive to the magnetic field parallel to the sensor chip surface for non-contact angular position sensing applications. The Vertical Trench Hall-Effect Device is built on SOI wafer which is produced by silicon direct bonding technology using bulk micromachining, where buried $SiO_2$ layer and surround trench define active device volume. Sensitivity up to 150 V/AT is measured.

• 센서학회지
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• 제23권6호
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• pp.392-396
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• 2014

The 2-dimensional silicon vertical Hall devices, which are sensitive to X,Y components of the magnetic field parallel to the surface of the chip, are fabricated using a modified bipolar process. It consists of the thin p-layer at Si-$SiO_2$ interface and n-epi layer to improve the sensitivity and influence of interface effect. Experimental samples are a sensor type K with and type J without $p^+$ isolation dam adjacent to the center current electrode. The results for both type show a more high sensitivity than the former's 2-dimensional vertical Hall devices and a good linearity. The measured non-linearity is about 0.8%. The sensitivity of type J and type K are about 66 V/AT and 200 V/AT, respectively. This sensor's behavior can be explained by the similar J-FET model.

• 센서학회지
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• 제20권4호
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• pp.260-265
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• 2011

The silicon vertical hall devices are fabricated using a modified bipolar process. It consists of the thin p-layer at Si-$SiO_2$, interface and n-epi layer without $n^+$buried layer to improve the sensitivity and influence of interface effects. Experimental samples are a sensor type I with and type H without p+isolation dam adjacent to the center current electrode. The experimental results for both type show a more high current-related sensitivity than the former's vertical hall devices. The sensitivity of type H and type I are about 150 V/AT and 340 V/AT, respectively. This sensor's behavior can be explained by the similar J-FET model.