• The KIPS Transactions:PartC
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• v.11C no.7 s.96
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• pp.951-958
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• 2004

Nowadays NGN is developed for supporting the e-Commerce, Internet trading, e-Government, e-mail, virtual-life and multimedia. Internet gives us the benefit of remote access to the information but causes the attacks that can break server and modify information. Since 2000 Nimda, Code Red Virus and DSoS attacks are spreaded in Internet. This attack programs make tremendous traffic packets on the Internet. In this paper, we designed and developed the Bandwidth Controller in the gateway systems against the bandwidth saturation attacks. This Bandwidth con-troller is implemented in hardware chipset(FPGA) Virtex II Pro which is produced by Xilinx and acts as a policing function. We reference the TBF(Token Bucket Filter) in Linux Kernel 2.4 and implemented this function in HDL(Hardware Description Language) Verilog. This HDL code is synthesized in hardware chipset and performs the gigabit traffic in real time. This policing function can throttle the traffic at the rate of band width controlling policy in bps speed.

• Journal of Advanced Navigation Technology
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• v.23 no.2
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• pp.134-141
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• 2019

Radar systems are divided into the pulse Doppler (PD) radar and the frequency modulated continuous wave (FMCW) radar depending on the transmission waveform. In particular, the PD radar is advantageous for long-range target detection, and the FMCW radar is suitable for short-range target detection. In this paper, we present design and implementation results for a multi-mode radar signal processor (RSP) that can support both PD and FMCW radar systems to detect unmanned aerial vehicles (UAVs) at short distances as well as long distances. The proposed radar signal processor can be implemented based on Altera Cyclone-IV FPGA with 19,623 logic elements, 9,759 registers, and 25,190,400 memory bits. The logic elements and registers of the proposed radar signal processor are reduced by approximately 43% and 30%, respectively, compared to the sum of logic elements and registers of the conventional PD radar and FMCW radar signal processor.

• Journal of IKEEE
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• v.25 no.4
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• pp.762-765
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• 2021

In this paper, an automotive ECU (electronic control unit) with Kalman filter accelerator is designed and implemented. RISC-V is exploited as a processor core. Accelerator for Kalman filter matrix operation, CAN (controller area network) controller for in-vehicle network, and LIN (local interconnect network) controller are designed and embedded. Kalman filter operation consists of time update process and measurement update process. Current state variable and its error covariance are estimated in time update process. Final values are corrected from input measurement data and Kalman gain in measurement update process. Usually floating-point multiplication is exploited in software implementation, but fixed-point multiplier considering accuracy analysis is exploited in this paper to reduce hardware area. In 28nm silicon fabrication, its operating frequency, area, and gate counts are 100MHz, 0.37mm², and 760k gates, respectively.

• Journal of Advanced Navigation Technology
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• v.24 no.2
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• pp.85-91
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• 2020

Recently, a multi-mode radar system was designed for efficient operation of unmanned aerial vehicles (UAVs) in various environments, which has the advantage of being able to integrate and utilize methods of the pulse Doppler (PD) radar and the frequency modulated continuous wave (FMCW) radar. For the range detection part of the multi-mode radar signal processor (RSP), the hardware structure using the FFT processor and the IFFT processor is required to be designed in a way that improves efficiency on the area side. In addition, given the radar application environment that requires a variety of distance resolutions, FFT processors need to support variable-length operations. In this paper, the FFT processor and IFFT processor in multi-mode RSP range estimation are designed and proposed as hardware for a single FFT processor that supports variable length operation of 16-1024 points. The proposed FFT processor designed in hardware description language (HDL) and can be implemented with 7,452 logic elements and 5,116 registers.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.58-63
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• 2013

This paper presents a transceiver design for DisplayPort interface using an optical channel. By converting the electronic channel to the optical channel, the DisplayPort's main channel can provide a high-speed data transmission for long distance. The design converting the electronic channel to the optical channel in the main channel and AUX channel of the DisplayPort is presented in this paper. Futhermore, the HPD signal transmission by using AUX channel is proposed. In order to minimize power consumption, this paper also proposed a method of controlling the TX block in the main link. The proposed system is designed by a FPGA and an optical module. The FPGA used 651 ALUT(adaptive look-up table)s, 511 resisters and 324 block memory bits. The maximum operating rate of the FPGA is 250MHz. With the proposed power control scheme, 740mW of power dissipation reduction can be achieved at the main link optical TX module.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.91-105
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• 2016

Carbon Nanotube Field-Effect Transistors (CNTFETs) have been studied as candidates for post Si CMOS owing to the better electrostatic control and high mobility. To enhance the immunity against short - channel effects (SCEs), the novel channel and gate engineered architectures have been proposed to improve CNTFETs performance. This work presents a comprehensive study of the influence of channel and gate engineering on the CNTFET switching, high frequency and circuit level performance of carbon nanotube field-effect transistors (CNTFETs). At device level, the effects of channel and gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. This model is based on two-dimensional non-equilibrium Green's functions (NEGF) solved self - consistently with Poisson's equations. It is revealed that hetero - material - gate and lightly doped drain and source CNTFET (HMG - LDDS - CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, improve the switching speed, and is more suitable for use in low power, high frequency circuits. At circuit level, using the HSPICE with look - up table(LUT) based Verilog - A models, the impact of the channel and gate engineering on basic digital circuits (inverter, static random access memory cell) have been investigated systematically. The performance parameters of circuits have been calculated and the optimum metal gate workfunction combinations of ${\Phi}_{M1}/{\Phi}_{M2}$ have been concluded in terms of power consumption, average delay, stability, energy consumption and power - delay product (PDP). In addition, we discuss and compare the CNTFET-based circuit designs of various logic gates, including ternary and binary logic. Simulation results indicate that LDDS - HMG - CNTFET circuits with ternary logic gate design have significantly better performance in comparison with other structures.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.55-62
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• 2007

This paper proposes a defective pixel detection algorithm and its hardware structure for CCD/CMOS image sensor. In previous algorithms, the characteristics of image have not been considered. Also, some algorithms need quite a time to detect defective pixels. In order to make up for those disadvantages, the proposed defective pixel detection method detects defective pixels efficiently by considering the edges in the image and verifies them using several frames while checking scene-changes. Whenever scene-change is occurred, potentially defective pixels are checked and confirmed whether it is defective or not. Test results showed that the correct detection rate in a frame was increased 6% and the defective pixel verification time was decreased 60%. The proposed algorithm was implemented with verilog HDL. The edge indicator in color interpolation block was reused. Total logic gate count was 5.4k using 0.25um CMOS standard cell library.

• Journal of Advanced Information Technology and Convergence
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• v.9 no.1
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• pp.115-125
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• 2019

In this paper, the image is received from the camera and the lane is sensed. There are various ways to detect lanes. Generally, the method of detecting edges uses a lot of the Sobel edge detection and the Canny edge detection. The minimum use of multiplication and division is used when designing for the hardware configuration. The images are tested using a black box image mounted on the vehicle. Because the top of the image of the used the black box is mostly background, the calculation process is excluded. Also, to speed up, YCbCr is calculated from the image and only the data for the desired color, white and yellow lane, is obtained to detect the lane. The median filter is used to remove noise from images. Intermediate filters excel at noise rejection, but they generally take a long time to compare all values. In this paper, by using addition, the time can be shortened by obtaining and using the result value of the median filter. In case of the Sobel edge detection, the speed is faster and noise sensitive compared to the Canny edge detection. These shortcomings are constructed using complementary algorithms. It also organizes and processes data into parallel processing pipelines. To reduce the size of memory, the system does not use memory to store all data at each step, but stores it using four line buffers. Three line buffers perform mask operations, and one line buffer stores new data at the same time as the operation. Through this work, memory can use six times faster the processing speed and about 33% greater quantity than other methods presented in this paper. The target operating frequency is designed so that the system operates at 50MHz. It is possible to use 2157fps for the images of 640by360 size based on the target operating frequency, 540fps for the HD images and 240fps for the Full HD images, which can be used for most images with 30fps as well as 60fps for the images with 60fps. The maximum operating frequency can be used for larger amounts of the frame processing.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.9
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• pp.2109-2116
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• 2014

This paper presents the implementation and design of the advanced WI-FI systems with beam-forming antenna that radiate their power to the direction of user equipment to improve the overall throughput, contrast to the general WI-FI systems equipped with omni-antenna. The system consists of patch array antenna, DSP, FPGA, and Qualcomm's commercial chip. The beam-forming system on the FPGA utilizes the packet information from Qualcomm's commercial chip to control the phase shifters and attenuators of the patch array antenna. The PCI express interface has been used to maximize the communication speed between DSP and FPGA. The directions of arrival of users are managed using the database, and each user is distinguished by the MAC address given from the packet information. When the system wants to transmit a packet to one user, it forms beams to the direction of arrival of the corresponding user stored in the database to maximize the throughput. Directions of arrival of users are estimated using the received preamble in the packet to make its SINR as high as possible. The proposed beam-forming system was implemented using an FPGA and Qualcommm's commercial chip together. The implemented system showed considerable throughput improvement over the existing general AP system with omni-directional antenna in the multi-user communication environment.