• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.584-586
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• 2017

In this paper we provide a unified crypto core that integrates lightweight symmetric cryptography and authentication. The crypto core implements a unified 128 bit key architecture of PRESENT encryption algorithm and a new lightweight encryption algorithm. The crypto core also consist of an authentication unit which neglects the use of hashing algorithms. Four algorithms are used for authentication which come from the Hopper-Blum (HB) and Hopper-Blum-Munilla-Penado (HB-MP) family of lightweight authentication algorithms: HB, HB+, HB-MP and HB-MP+. A unified architecture of these algorithms is implemented in this paper. The unified cryptosystem is designed using Verilog HDL, simulated with Modelsim SE and synthesized with Xilinx Design Suite 14.3. The crypto core synthesized to 1130 slices at 189Mhz frequency on Spartan6 FPGA device.

• Journal of Advanced Information Technology and Convergence
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• v.10 no.2
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• pp.153-166
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• 2020

DDI(Display Driver IC) are used to drive numerous pixels that make up display. For stable driving of DDI, it is necessary to attach a protective film to shield electromagnetic waves. When the protective film is attached, defects often occur if the film is inclined or the center point is not aligned. In order to minimize such defects, an algorithm for correcting the center point and the inclined angle using camera image information is required. This technology detects the corner coordinates of the protective film by image processing in order to correct the positional defects where the protective film is attached. Corner point coordinates are detected using an algorithm, and center point position finds and correction values are calculated using the detected coordinates. LUT (Lookup Table) is used to quickly find out whether the angle is inclined or not. These algorithms were described by Verilog HDL. The method using the existing software requires a memory to store the entire image after processing one image. Since the method proposed in this paper is a method of scanning by adding a line buffer in one scan, it is possible to scan even if only a part of the image is saved after processing one image. Compared to those written in software language, the execution time is shortened, the speed is very fast, and the error is relatively small.

• Journal of Internet Computing and Services
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• v.10 no.1
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• pp.1-9
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• 2009

In this paper, A pipeline structured-degree computationless modified Euclidean (PS-DCME) algorithm is proposed, which can be used for a RS(23,17) decoder for MB-OFDM system. PS-DCME algorithm requires a state machine instead of the degree computation and comparison circuits, so that the hardware complexity of the decoder can be reduced and high-speed decoder can be implemented. We have implemented a RS(23,17) decoder with PS-DCME using Verilog HDL and synthesized with Samsung 65nm library. From synthesis results, it can operate at clock frequency of 250MHz, and gate count is 19,827.

• Journal of IKEEE
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• v.24 no.2
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• pp.665-668
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• 2020

When a node in automotive CAN bus is hacked, such node should be blocked to prevent severe danger in the car. In order to do that, such node should be uniquely identified. However, there is no way to identify individual nodes in a CAN bus. In this paper, a physical layer security method is proposed where individual nodes are identified by assigning unique ID to the nodes during booting process. The proposed method was implemented in a CAN controller using Verilog HDL, and it is verified that the node ID auto-setting and internal attack defense are successfully performed.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.185-185
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• 2000

This paper designs an interference mitigation filter for GPS receiver using a time-domain signal processing techniques (Adaptive Transversal filter). ATF is designed using verilog and simulated using COSSAP for evaluating its performance.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.7
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• pp.1581-1588
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• 2010

Most digital cameras use a single image sensor with Color Filter Array(CFA) for the advantage of costs and speed. The various color interpolation(demosaicing) algorithms are researched to reconstruct a full representation of the image. In this paper, we proposed a method of demosaicing about using weighted directional filter for vertical, horizontal, and diagonal direction edge. The method considered the efficiency of hardware resources for hardware implementation. The performance of proposed method was confirmed by comparing the conventional method in experiments using 24 Kodak test images. The proposed method was designed by Verilog HDL and was verified by using Virtex4 FPGA boards and CMOS Image Sensor.

• The Journal of the Korea Contents Association
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• v.10 no.8
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• pp.59-65
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• 2010

This paper proposes an implementation of a hardware module for transmitting MPEG-2 TS data over the internet protocol (IP)-based network. This implementation consists of two modules; one is an encapsulation module which bridges between n TS packets, where $1\;{\leq}\;n\;{\leq}\;7$, and an IP packets, the other is a packet conversion module which extracts an DSM-CC PS packet from consecutive TS packets and then reconstructing an IP packet. So, these IP packets are carried over 150 megabits per second. Although overall work flow of the proposed DeMUX is based on the reference design of ALTERA, the DeMUX is enhanced by modifying it and performs more functions by adding a packet conversion module. The DeMUX is described by Verilog-HDL (hardware description language) and shows the faithful functionality and throughput through the simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.46-51
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• 2010

We propose the novel Hybrid bus arbitration policy that prevents a priority monopolization presented in fixed priority and effectively assigns a priority to each master by mixing fixed priority and round-robin arbitrations. The proposed arbitration policy and the others were implemented through Verilog and mapped the design into Hynix 0.18um technology and compared about gate count and area overhead. In the results of performance analysis, we confirm that our proposed policy outperforms the others and effectively controls the bus utilization.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.10a
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• pp.648-651
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• 2001

This paper describes the 8-error-correction (204, 188) Reed-Solomon Decode. over GF(2$^{8}$ ) for a satellite communication. It is synthsized using a CMOS library. Decoding algorithm of Reed-Solomon codes consists of four steps which are to compute syndromes, to find error-location polynomial, to decide error-location, and to slove error-values. The decoder is designed using Modified Euclid algorithm in this paper. First of all, The functionalities of the circuit are verified through C++ programs, and then it is designed in Verilog HDL. It is verified through the logic simulations of each blocks. Finally, The Reed-Solomon Decoder is synthesized with Synopsys Tool.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.430-432
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• 2015

This paper describes a hardware implementation of ultra-lightweight block cipher algorithm PRESENT-80/128 that supports for two master key lengths of 80-bit and 128-bit. The PRESENT algorithm that is based on SPN (substitution and permutation network) consists of 31 round transformations. A round processing block of 64-bit data-path is used to process 31 rounds iteratively, and circuits for encryption and decryption are designed to share hardware resources. The PRESENT-80/128 crypto-processor designed in Verilog-HDL was verified using Virtex5 XC5VSX-95T FPGA and test system. The estimated throughput is about 550 Mbps with 275 MHz clock frequency.