• 소성∙가공
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• 제7권5호
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• pp.450-458
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• 1998

The high temperature deformation behavior of Al 5083 alloy has been studied in the temperature range of 350 to 520 ${\circ}C$ and strain rate range of 0.2 to 3.0/sec by torsion test. The strain rate sensitivity(m) of the material was evaluated and used for estabilishing power dissipation maps following the dynamic material model. These maps show the variation of efficiency of power dissipation(${\eta}$=2m/(2m+1)) with temperature and strain rate. Hot restoration of dynamic recrystallization (DRX) was analyzed from the flow curve, deformed microstructure, and processing maps during hot deformation. Also, the effect of deformation strain on the efficiency of power dissipation of the alloy was analysed using the processing maps. Moreover relationship between the hot-ductility and efficiency of power dissipation of the alloy depending on thmperature and strain rate was studied using the Zener-Hollomon parameter(Z=${\varepsilon}$exp(Q/RT) It is found that the maximum efficiency of power dissipation for DRX in Al 5083 alloy is about 74.6 pct at the strain of 0.2. The strain rate and temperature at which the efficiency peak occurred in the DRX domain is found to be ∼0.1/sec and ∼450${\circ}C$ respectively.

• 디지털콘텐츠학회 논문지
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• 제9권3호
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• pp.471-481
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• 2008

전력소모를 고려한 테스트 스케줄링은 회로의 복잡도가 높은 SoC 시스템을 테스트할 경우 제한된 전력 소모량 내에서 고장 검출율을 높일 수 있고 테스트 시간을 단축 할 수 있는 효과적인 방법이다. 본 논문에서는 제한된 전력소모량 내에서 효율적으로 테스트를 수행하기 위한 테스트 자원의 모델링 방법 및 테스트 스케줄링 알고리듬을 제안하고 그 유효성을 검증한다. 테스트 자원의 모델링 방법으로는 전력사용량의 최고점과 차고점을 이용한 방법 및 소모 전력의 변화량에 따라 테스트 자원을 분할하는 방법을 제시한다. 또한 테스트 자원과 코어의 상관관계를 이용하여 동시 사용가능한 최대 코어 수를 생성하는 확장나무성장 그래프 생성 알고리듬 및 전력의 최적화가 가능한 전력 소모량 변이 그래프 생성 알고리듬으로 구성된 휴리스틱(heuristic) 테스트 스케줄링 알고리듬을 제안하고 이전의 알고리듬과 비교한다.

• 대한설비공학회지:설비저널
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• 제17권2호
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• pp.131-139
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• 1988

The thermoacoustic oscillation induced in an air column with variable cross section area is investigated theoretically and experimentally. The onset condition of the oscillation is derived by equating the acoustic power production to the power dissipation. The power production at the heater is predicted by using the efficiency factor obtained by heat transfer analysis for a single wire in a uniform cross flow and considering the interference between heater wires. The power dissipation is estimated by measuring the attenuating coefficient from the pressure decay curve. The theoretical prediction to the onset condition of the oscillation is confirmed experimentally. The effect of the variation of the column cross section area on the onset condition is presented.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.703-706
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• 1998

This paper presents an efficient substrate-bias generator(SBG)for low-power, high-density DRAM's The proposed SBG can supply stable voltage with switching the supply voltage of driving circuit, and it can substitude the small capacitance for the large capacitance. The charge pumping circuit of the SBG suffere no VT loss and is to be applicable to low-voltage DRAM's. Also it can reduce the power consumption to make VBB because of it's high pumping efficiency. Using biasing voltage with positive temperature coefficient, VBB level detecting circuit can detect constant value of VBB against temperature variation. VBB level during VBB maintaining period varies 0.19% and the power dissipation during this period is 0.16mw. Charge pumping circuit can make VBB level up to -1.47V using VCC-1.5V, and do charge pumping operation one and half faster than the conventional ones. The temperature dependency of the VBB level detecting circuit is 0.34%. Therefore the proposed SBG is expected to supply a stable VBB with less power consumption when it is used in low power DRAM's.

• 한국통신학회논문지
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• 제37권8A호
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• pp.712-719
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• 2012

본 논문은 오디오 신호 처리 시스템의 저속 고해상도 ADC를 위해 설계된 CMOS 단일비트 3차 델타시그마 변조기를 설계하였다. 변조기 내 적분기에 사용되는 연산증폭기의 전력소모를 감소시키기 위해서 연산증폭기내 바이어스 전류원에 차단/동작 기능을 하는 스위치를 장착시켰다. 또한 변조기내 스위치의 위치를 최적화 하여 기존의 스위칭 방식에서 발생하는 주파수 특성 변화를 최소화하였다. 단일 비트 3차 델타시그마 변조기 구조를 선택하였으며, 제안한 델타 시그마 변조기의 성능측정결과 전원 전압 3.3V, 샘플링 주파수 6.4MHz, 입력주파수 20KHz에서 17.1mW의 전력소모를 나타냈다. SNDR은 84.3dB, 유효비트수는 13.5비트를 나타내었다.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2005년도 춘계학술대회
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• pp.516-519
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• 2005

The pilot tidal current power plant is to be constructed at the Uldolmok between Chindo and Haenam, during next year. and extensive coastal engineering research works have been carried out. In this paper we describes some observation results of the tide and tidal current. as well as modeling work in order to investigate the tide and tidal current regime change in relation to the tidal current power plant (TCPP) construction. The special modeling skill in order to consider the turbine operation in the TCPP is developed and applied to the estimation for the flow regime change by the simple layout of the tidal current power plant.

• 신재생에너지
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• 제1권2호
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• pp.73-78
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• 2005

The pilot tidal current power plant is to be constructed at the Uldolmok between Chindo and Haenam, during next year, and extensive coastal engineering research works have been carried out. In this paper we describes some observation results of the tide and tidal current, as well as modeling work in order to investigate the tide and tidal current regime change In relation to the tidal current power plant [TCPP] construction. The special modeling skill in order to consider the turbine operation in the TCPP is developed and applied to the estimation for the flow regime change by the simple layout of the tidal current power plant.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 E
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• pp.2110-2113
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• 1999

This paper describes the initial characteristics of turbine generators at the Taean thermal power plant #4 and Wolsong nuclear power plant #2. The turbine generators had been in service for two years. The insulation diagnostic tests included measurements of insulation resistance, polarization index, ac current, dissipation factor($tan{\delta}$) and partial discharges (PD). The values of ac current and tan a were measured by Schering bridge. PD measurements were conducted using digital PD detector. The variation of $tan{\delta}$ and PD was confirmed in two generator stator insulations.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.707-710
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• 1998

This paper presents a new voltage down converter(VDC) for low power, high speed DRAM. This VDC Consists of RVG(Reference Voltage Generator) and Driver Circuit. And it is independent of temperature variation, and Supply Voltage. Using weak inversion region, this RVG dissipates low power. Internal Voltage Source of this VDC is stable in spite of high speed operation of memory array. This circuit is designed with a $0.65\mu\textrm{m}$ nwell CMOS technology. In HSPICE simulation results, Temperature dependency of this RVG is $20\muV/^{\circ}C,$ supply voltage dependency is $\pm0.17%,$ $VCC=3.3V\pm0.3V,$ and current dissipation is $5.22\muA.$ Internal voltage source bouncing of this VDC is smaller than conventional VDC.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권4호
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• pp.397-404
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• 2012

Thermal generation by power dissipation of the highly integrated System on Chip (SoC) device is irregularly distributed on the intra chip. It leads to thermal increment of the each thermally different region and effects on the propagation timing; consequently, the timing violation occurs due to the misestimated number of buffers. In this paper, the timing budgeting methodology considering thermal variation which contains buffer insertion with wire segmentation is proposed. Thermal aware LUT modeling for cell intrinsic delay is also proposed. Simulation results show the reduction of the worst delay after implementing thermal aware buffer insertion using by proposed wire segmentation up to 33% in contrast to the original buffer insertion. The error rates are measured by SPICE simulation results.