• Journal of Electrical Engineering and Technology
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• 제9권5호
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• pp.1632-1642
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• 2014

This paper presents an interleaved resonant converter to reduce the voltage stress of power MOSFETs and achieve high circuit efficiency. Two half-bridge converters are connected in series at high voltage side to limit MOSFETs at $V_{in}/2$ voltage stress. Flying capacitor is used between two series half-bridge converters to balance two input capacitor voltages in each switching cycle. Variable switching frequency scheme is used to control the output voltage. The resonant circuit is operated at the inductive load. Thus, the input current of the resonant circuit is lagging to the fundamental input voltage. Power MOSFETs can be turn on under zero voltage switching. Two resonant circuits are connected in parallel to reduce the current stress of transformer windings and rectifier diodes at low voltage side. Interleaved pulse-width modulation is adopted to decrease the output ripple current. Finally, experiments are presented to demonstrate the performance of the proposed converter.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• 제3B권1호
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• pp.10-15
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• 2003

This paper presents the digital computer performance evaluations of the three-phase self-excited induction generator (SEIG) driven by the variable speed prime mover such as the wind turbine using the nodal admittance approach steady-state frequency domain analysis with the experimental results. The three-phase SEIG setup is implemented for small-scale rural renewable energy utilizations. The experimental performance results give a good agreement with those ones obtained from the digital computer simulation. Furthermore, a feedback closed-loop voltage regulation of the three-phase SEIG as a power conditioner which is driven by a variable speed prime mover employing the static VAR compensator (SVC) circuit composed of the thyristor phase controlled reactor (TCR) and the thyristor switched capacitor(TSC) is designed and considered herein for the wind-turbine driven the power conditioner. To validate the effectiveness of the SVC-based voltage regulator of the terminal voltage of the three-phase SEIG, an inductive load parameter disturbances in stand-alone are applied and characterized in this paper. In the stand-alone power utilization system, the terminal voltage response and thyristor triggering angle response of the TCR are plotted graphically. The simulation and the experimental results prove the effectiveness and validity of the proposed SVC which is controlled by the Pl controller in terms of fast response and high performances of the three-phase SEIG driven directly by the rural renewable energy utilization like a variable-speed prime mover.

• 대한전자공학회논문지
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• 제5권2호
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• pp.28-45
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• 1968

本 解說은 "電壓으로 調節되는 可變容量에 依한 同調(Voltage Variable Capactior Tuning)"의 發達史, 理論, 特性, 應用 및 將來展望에 對해서 言及한다. 모든 式들은 指數則函數, 卽 Xm에 比例하는 不純物分布 및 (V+V0)-n에 比例하는 差캐퍼시턴스의 두 가지 一般指數項으로 記述되는데 이 指數項들의 役割에 對해서는 "電壓으로 調節되는 發振器(VOC)"의 理論, 溫度드리프트 및 直線性과 FM變調器의 混變調에서 說明된다. 또한 本文의 內容을 補强하기 위해 많은 論文 및 報告文들로부터 重要結果를 引用하며 本文 전체에 걸쳐 n=2 일때의 要求事項에 對해서 풀이한다.

• 전력전자학회논문지
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• 제27권5호
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• pp.417-424
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• 2022

This study proposes a current-balancing technique for an interleaved buck converter using a variable inductor and a snubber capacitor. The proposed scheme balances the inductor current by using the variable inductor and enables zero voltage switching under all load ranges. With the variable inductor, the ripple of inductor current changes according to load variation. In addition, a 1.6 kW prototype is built to verify the validity of the proposed scheme, and the experimental results are successfully obtained.

• Journal of Power Electronics
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• 제9권6호
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• pp.823-834
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• 2009

This paper proposes a high-efficiency single-stage ac/dc converter. The proposed converter features low voltage stresses and reduced switching losses. It operates at the boundary of discontinuous- and continuous-conduction modes by employing variable switching frequency control. The turn-on switching loss of the switch can be reduced by turning it on when the voltage across it is at a minimum. The voltage across the bulk capacitor is independent of the output loads and maintained within the practical range for the universal line input, so the problem of high voltage stress across the bulk capacitor is alleviated. Moreover, the voltage stress of the output diodes is clamped to the output voltage, and the output diodes are turned off at zero-current. Thus, the reverse-recovery related losses of the output diodes are eliminated. The operational principles and circuit analysis are presented. A prototype circuit was built and tested for a 150 W (50V/3A) output power. The experimental results verify the performance of the proposed converter.

• ETRI Journal
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• 제31권6호
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• pp.717-724
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• 2009

This paper describes a 1.2 V 12 b 60 MS/s CMOS analog front-end (AFE) employing low-power and flexible design techniques for image signal processing. An op-amp preset technique and programmable capacitor array scheme are used in a variable gain amplifier to reduce the power consumption with a small area of the AFE. A pipelined analog-to-digital converter with variable resolution and a clock detector provide operation flexibility with regard to resolution and speed. The AFE is fabricated in a 0.13 ${\mu}m$ CMOS process and shows a gain error of 0.68 LSB with 0.0352 dB gain steps and a differential/integral nonlinearity of 0.64/1.58 LSB. The signal-to-noise ratio of the AFE is 59.7 dB at a 60 MHz sampling frequency. The AFE occupies 1.73 $mm^2$ and dissipates 64 mW from a 1.2 V supply. Also, the performance of the proposed AFE is demonstrated by an implementation of an image signal processing platform for digital camcorders.

• Journal of Power Electronics
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• 제3권3호
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• pp.185-196
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• 2003

In this paper, the single-phase static VAR compensator (SVC) is applied to regulate and stabilize the generated terminal voltage of the single-phase self-excited induction generator (single-phase SEIG) driven by a variable-speed prime mover (VSPM) under the conditions of the independent inductive load variations and the prime mover speed changes The conventional fixed gain PI controller-based feedback control scheme is employed to adjust the equivalent capacitance of the single-phase SVC composed of the fixed excitation capacitor FC in parallel with the thyristor switched capacitor TSC and the thyristor controlled reactor TCR The feedback closed-loop terminal voltage responses in the single-phase SEIG coupled by a VSPM with different inductive passive load disturbances using the single-phase SVC with the PI controller are considered and discussed herem. A VSPM coupled the single-phase SEIG prototype setup is established. Its experimental results are illustrated as compared with its simulation ones and give good agreements with the digital simulation results for the single-phase SEIG driven by a VSPM, which is based on the SVC voltage regulation feedback control scheme.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2018년도 전력전자학술대회
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• pp.75-77
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• 2018

최근 다양한 산업응용분야에서 가변커패시터의 필요성은 점점 증가하고 있다. 특히 고전력 RF플라즈마 시스템에서 임피던스 정합 회로에 사용되는 가변커패시터는 빠른 고전압 차단능력이 요구된다. 본 논문에서는 RF플라즈마 시스템의 임피던스 정합 회로에 활용되는 단방향 스위치를 사용한 전기적 가변 캐패시터 (Electrical Variable Capacitor, 이하 EVC) 회로의 전압 스트레스를 저감하는 방법에 대해서 제안한다. 제안된 방법은 13.56Mhz의 주파수와 1kW이상의 고전력 RF플라즈마 시스템에서 단방향 스위치의 전압 스트레스를 양방향스위치를 사용한 EVC 회로를 활용하여 저감한다. 본 논문에서 제안된 방법으로 전압 스트레스가 감소하여 EVC 회로를 고전력 초고속 RF플라즈마 시스템의 임피던스 정합 회로에 좀 더 효과적 으로 적용할 수 있게 된다. 시뮬레이션 및 실험을 통해 EVC 회로의 스위치에 걸리는 전압 스트레스가 40%이상 저감되는 것을 검증하였다.

• 전기전자학회논문지
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• 제28권1호
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• pp.72-77
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• 2024

본 논문에서는 최근 요구되는 이동통신 서비스의 다양한 주파수 대역 요구를 충족시키기 위해 3중 모드 주파수 가변 필터를 제안한다. 이 필터는 가변 커패시터를 활용하여 공진 주파수를 조절할 수 있는 튜닝 가능한 구조를 가지고 있다. 품질 계수를 향상하기 위해 SIW (Substrate Integrated Waveguide) 구조를 도입하였고, 중앙에 위치한 원형 홀을 통해 세 개의 공진 모드를 유발하는 구조를 구현하였다. 가변 커패시터에 의해 변화에 따른 전계분포와 공진 주파수의 변화를 EM 전파해석툴인 HFSS를 사용하여 시뮬레이션하였으며, 3중 모드의 전계분포와 공진 주파수의 변화를 확인하였다.

• 대한전자공학회논문지SD
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• 제46권1호
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• pp.45-51
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• 2009

심장박동 조절장치를 위한 저전압 저전력 전단 처리기를 제안한다. 제안된 회로는 80 Hz에서 120 Hz의 대역폭을 가지는 4차의 스위치드 커패시터 필터와 0 dB에서 24 dB까지 0.094 dB 간격으로 전압이득의 조절이 가능한 전압증폭기를 구현하였다. 낮은 전압에서 동작하고, 전력소모를 극소화하기 위해서 인버터 기반의 스위치드 커패시터 회로를 사용하였으며, 인버터가 가지는 작은 전압이득을 보상하기 위해서 상호상관 기법을 사용하였다. 제안된 회로는 $0.35-{\mu}m$ CMOS 공정을 이용하여 구현되었으며, 5kHz의 샘플링 주파수에서 80-dB의 SFDR을 가진다. 이때 전력소모는 1 V의 전원전압에서 330 nW에 불과하다.