• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.1
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• pp.183-190
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• 2010

We propose an eFuse one-time programmable (OTP) memory cell based on a logic process, which is programmable by an external program voltage. For the conventional eFuse OTP memory cell, a program datum is provided with the SL (Source Line) connected to the anode of the eFuse going through a voltage drop of the SL driving circuit. In contrast, the gate of the NMOS program transistor is provided with a program datum and the anode of the eFuse with an external program voltage (FSOURCE) of 3.8V without any voltage drop for the newly proposed eFuse cell. The FSOURCE voltage of the proposed cell keeps either 0V or the floating state at read mode. We propose a clamp circuit for being biased to 0V when the voltage of FSOURCE is in the floating state. In addition, we propose a VPP switching circuit switching between the logic VDD (=1.8V) and the FSOURCE voltage. The layout size of the designed eFuse OTP memory IP with Dongbu HiTek's $0.15{\mu}m$ generic process is $359.92{\times}90.98{\mu}m^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.59-67
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• 2007

This paper presents a low power dual-level low voltage differential signaling (DLVDS) technique using current source switching for LCD driver ICs in portable products. The transmitter makes dual level signal that has two different level signal 400mVpp and 250mVpp while keeping the advantages of LVDS. The decoding circuit recovers the primary signal from DLVDS. The low power DLVDS is implemented using a $0.25{\mu}m$ CMOS process under 2.5V supply. The proposed circuit shows 800Mbps/2-line data rate and 9mW, 11.5mW power consumptions in transmitter and receiver, respectively. The proposed DLVDS scheme reduce power consumption dramatically compare with conventional one.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1868-1876
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• 2010

In this paper, we design a 256-bit EEPROM IP using only logic process-based devices. We propose EEPROM core circuits, a control gate (CG) and a tunnel gate (TG) driving circuit, to limit the voltages between the devices within 5.5V; and we propose DC-DC converters : VPP (=+4.75V), VNN (-4.75V), and VNNL (=VNN/3) generation circuit. In addition, we propose switching powers, CG_HV, CG_LV, TG_HV, TG_LV, VNNL_CG, VNNL_TG switching circuit, to be supplied for the CG and TG driving circuit. Simulation results under the typical simulation condition show that the power consumptions in the read, erase, and program mode are $12.86{\mu}W$, $22.52{\mu}W$, and $22.58{\mu}W$ respectively. Furthermore, the manufactured test chip operated normally and generated its target voltages of VPP, VNN, and VNNL as 4.69V, -4.74V, and -1.89V.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.12
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• pp.2366-2373
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• 2007

In this paper, a low-power and small-area asynchronous 1 kilobit EEPROM for passive UHF RFID tag chips is designed with $0.18{\mu}m$ EEPROM cells. As small area solutions, command and address buffers are removed since we design asynchronous I/O interface and data output buffer is also removed by using separate I/O. To supply stably high voltages VPP and VPPL used in the cell array from low voltage VDD, Dickson charge pump is designed with schottky diodes instead of a PN junction diodes. On that account, we can decrease the number of stages of the charge pump, which can decrease layout area of charge pump. As a low-power solution, we can reduce write current by using the proposed VPPL power switching circuit which selects each needed voltage at either program or write mode. A test chip of asynchronous 1 kilobit EEPROM is fabricated, and its layout area is $554.8{\times}306.9{\mu}m2$., 11% smaller than its synchronous counterpart.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.6
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• pp.57-65
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• 2007

This paper presents the design of single phase PFC(Power Factor Correction) using a DSP(TMS320F2812). In order to realize the proposed boost PFC converter in average current mode control, the DSP requires the A/D sampling values for a line input voltage, a inductor current, and the output voltage of the converter. Because of a FET switching noise, these sampling values contain a high frequency noise and switching ripple. The solution of A/D sampling keeps away from the switching point. Because the PWM duty is changed from 5% to 95%, we can#t decide a fixed sampling time. In this paper, the three A/D converters of the DSP are started using the prediction algorithm for the FET ON/OFF time at every sampling cycle(40 KHz). Implemented A/D sampling algorithm with only one timer of the DSP is very simple and gives the autostart of these A/D converters. From the experimental result, it was shown that the power factor was about 0.99 at wide input voltage, and the output ripple voltage was smaller than 5 Vpp at 80 Vdc output. Finally the parameters and gains of PI controllers are controlled by serial communication with Windows Xp based PC. Also it was shown that the implemented PFC converter can achieve the feasibility and the usefulness.