• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.445-448
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• 2000

This paper considers a scheduling algorithm for high-speed routers, where the router has an N x N port input-queued switch and the input queues are composed of N VOQ(Virtual Output Queue)s at each input port. The major concern of the paper is on the scheduling mechanism for the router. The paper discusses the preferred levels of the performance measures and then develope a non-linear mixed integer programming. Additionally, the paper suggests a heuristic scheduling algorithm for efficient and effective switching.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.9A
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• pp.973-982
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• 2004

High-speed scheduling algorithms are required for high-performance input-queued switches to achieve good performance. Various Round-Robin scheduling algonthms for Virtual-Output-Queue (VOQ) switch architectures have been proposed, hke iSLIP, DRRM (Dual Round-Robin Matching). iSLIP can achieve high performance and have already been implemented in hardware. DRRM has been proved to achieve better performance and simpler than iSLIP But neither iSLIP nor DRRM can efficiently solve the problem of the Round-Robm pointers' desynchronization. In this paper, we have proposed "Well-Regulated Pseudo-request Dual Round-Robin Matching" Algorithm. It is developed from DRRM, and can always keep the pointers' desynchronization. Since our algorithm is based on the Round-Robin scheduling, it is also simple to be implemented. And simulation results also show that our proposed algonthm performs pretty well under various, traffic models.

• ETRI Journal
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• v.40 no.3
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• pp.337-346
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• 2018

In this paper, we propose a grant-aware (GA) scheduling algorithm that can provide higher throughput and lower latency than a conventional dual round-robin matching (DRRM) method. In our proposed GA algorithm, when an output receives requests from different inputs, the output not only sends a grant to the selected input, but also sends a grant indicator to all the other inputs to share the grant information. This allows the inputs to skip the granted outputs in their input arbiters in the next iteration. Simulation results using OPNET show that the proposed algorithm provides a maximum 3% higher throughput with approximately 31% less queuing delay than DRRM.

• Proceedings of the Korean Information Science Society Conference
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• 2007.06d
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• pp.503-507
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• 2007

라우터는 여러 곳에서 들어오는 패킷들을 빠르게 전달하는 기능을 담당하는 네트워크 장비로서, 들어오는 패킷들이 공평하게 서비스 받을 수 있도록 큐 관리 알고리즘을 사용한다. 그런데 대부분의 라우터들은 HOL 블록킹 문제 때문에 버퍼를 입력 포트 쪽이 아닌 가상적으로 출력 포트 쪽에 정의하는 VOQ로 구현을 하였고, 패킷들이 공평하게 서비스 받기 위해 DRR 알고리즘으로 구현하는 경향이 있다. 이 논문에서는 기존의 DRR 알고리즘에서 패킷 서비스를 위한 경직된 조건에 유연성을 주어 기존의 DRR 알고리즘의 복잡도와 공평성을 유지하는 한편 패킷 서비스 성능을 높여주는 NDRR 알고리즘을 제안한다.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.884-887
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• 2002

This paper considers a scheduling problem of routers with VOQ(Virtual Output Queue)s, where the router has an N ${\times}$N port input-queued switch and each input queue is composed of N VOQs. The objective of the paper is to develope scheduling algorithms which minimize mean tardiness under a common due date. The paper characterizes the optimal solution properties. Based upon the characterization, a integer programming is formulated for the optimal solution and two optimal solution algorithms are developed for two special cases of 2 ${\times}$2 switch and N${\times}$N switch with identical traffic.

• Proceedings of the Korean Information Science Society Conference
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• 2002.10e
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• pp.127-129
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• 2002

NP Forum에서는 다양한 밴더의 네트워크 프로세서와 스위치 패브릭간에 물리적 인터페이스를 제공하기 위해 CSIX-L1(Common Switch Interface-Level 1 )인터페이스를 표준화하였다. IBM 네트워크 프로세서는 MPLS 및 VPN, VLAN, Security, Ipv6와 같은 다양한 어플리케이션과 TBI. SMII CMII. POS bus등 다양한 가입자 인터페이스를 지원하며, L2 기 반에서 2.5Gbps 이상의 패킷 처리를 수행하기 때문에 많은 시스템에 사용된다. 그러나 IBM네트워크 프로세서는 스위치 인터페이스로 DASL인터페이스를 사용한다. 따라서 DASL인 터페이스와 CSIX-L1 인터페이스를 정합하기 위해서는 IBM UDASL칩을 이용해 DASL인 터페이스를 UTOPIA-L3인터페이스로 변환해야 하며, 이것을 다시 CSIX-L1인터페이스로 변환해야 한다. 따라서 본 논문에서는 UTOPIA-L3인터페이스 패킷과 CSIX-L1인터페이스 프레임을 상호 변환하는 모듈을 설계하였으며, 32비트 데이터 버스와 최대 125MHz로클록을 사용해 최대 4Gbps의 패킷처리를 제공하도록 구현하였다. 또한 스위치 패브릭의 특정 포트에서 과잉 트래픽 전달로 인해 발생할 수 있는 블로킹을 방지하기 위해 네트워크 프로세서에게 3개의 Priority／최대 64개 포트수의 VOQ(Virtual Output Queue)를 제공하는 기법에 대해서 기술한다.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1847-1850
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• 2002

In this paper, MPLS Router module supporting Differentiated Service(Diffserv) for quality of Service (QoS) and High-speed switching is proposed and implemented. And we compare and analyze the proposed architecture with the conventional one in terms of CLR (Cell Loss Rate) and average delay. Switch is an extended system of Queue of each VOQ and PHB in the manner of Input Queuing for QoS. Algorithm, Priority-iSLIP is used for its scheduling algorithm. The proposed architecture is modeled in C++ and verified.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.7
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• pp.1393-1398
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• 2003

In this paper, we propose a new switch architecture with one schedule at k-time slots, which k means the allocated time slots for each schedule. A conventional switch system uses a single time slot per each schedule but the proposed switch system uses multiple time slots per each schedule. Both the conventional switch md the proposed switch have same throughput but our switch system occupies multiple cell time slots per each schedule and hence can be implemented in scheduler of simple circuitry compared to the conventional switch. The proposed scheduling method for switch system will be applicable in switch system with high-speed data link rate.

• Journal of Internet Computing and Services
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• v.5 no.3
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• pp.45-56
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• 2004

In this paper, we propose ATM switch architecture including ALL type 2 switch which can efficiently transmit low-bit rate data, even if the network has many endpoints. We simulate the architecture of ATM switch fabric that is modeled in computer program and analyze the performance according to offered loads. ATM switch proposed in this paper can support cell switching for all types of m cells which consist of ALL type 1. ALL type 2, ALL type 3/4 and ALL type 5 cells. We propose two switch fabric methods; One supports the ALL type 2 cell processing per input port, the other global ALL type 2 cell processing for every input port. The simulation results show that the latter is superior to the former. But the former has a merit for easy implementation and extensibility. In this paper, the AAL Type 2 switch module which adapts the former method is designed using VHDL language and implemented in FPGA chip. The designed AAL Type 2 switch module operates at 52MHz. The proposed ATM switch fabric is widely applicable to mobile communication, narrow band services over ATM network and wireless ATM as well as general ATM switching fabric.