• Proceedings of the KIEE Conference
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• 1983.07a
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• pp.247-249
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• 1983

분 논문에서는 순차제어기 설계 과정을 전산화함과 동시에 여러 종류의 순차 제어 방식에도 일반적으로 적용될 수 있는 VLSI회로 설계법을 제안하고 있다. 특히 VLSI설계에 적합한 회로를 구성하기 위해 최소 구성의 기억 소자를 사용하여 이에 맞는 설계 프로그램을 개발하여 응용 결과를 기존의 방법과 비교하여 보았다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.3
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• pp.26-33
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• 1984

This paper proposes a new LSI/VLSI logic design structure which improves shift register latches in conventional LSSD. Test patterns are easily generated and fault coverage is enhanced by using the design structure. The new parallel shift register latch can be applied to the design of easily testable PLA's. In this case, the number of test patterns is decreased and decoders which are added to the feedback inputs in conventional PLA's using LSSD are not necessary.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.2
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• pp.269-277
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• 1986

This paper proposes a new algorithmic state machine(ASM) chart and a new hardware description for automatic logic design of VLSI. To describe the behavioral characteristics of the design specification, the conventional ASM chart is modified, and a new hardware description language, SDL, is proposed. The SDL is one-to-one correspondent to the proposed ASM chart symbol, and can be used in a hierachical design of VLSI. As a design example, we obtain a logic circuit diagram of gate lebel utilizing a SDL hardware compiler after drawing an ASM chart and describing in SDL.

• The Magazine of the IEIE
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• v.25 no.5
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• pp.31-41
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• 1998

With the advent of portable electronic systems, power consumption has recently become a major issue in circuit and system design. Furthermore, the sophisticated fabrication technology makes it possible to embed more functions and features in a VLSI chip, consequently calling for both higher performance and lower power to deal with the ever growing complexity of system algorithms than in the past. VLSI designers should cope with two conflicting constraints, high performance and low power, offering an optimum trade off of these constraints to meet requirements of system. Historically, VLSI designers have focused on performance improvement, and power dissipation was not a design criteria but an afterthought. This design paradigm should be changed, as power is emerging as the most critical design constraint. In VLSI design, low power design can be accomplished through many ways, for instance, process, circuit/logic design, architectural design, and etc.. In this paper, a few low power design examples, which have been used in 8 bit micro-controller core, and can be used also in 4/16/32 bit micro-controller cores, are presented in the areas of circuit, logic and architectural design. We first propose a low power guidelines for micro-controller design in SAMSUNG, and more detailed design examples are followed applying 4 specific design guidelines. The 1st example shows the power reduction through reduction of number of state clocks per instruction. The 2nd example realized the power reduction by applying RISC(Reduced Instruction Set Computer) concept. The 3rd example is to optimize the algorithm for ALU(Arithmetic Logic Unit) to lower the power consumption, Lastly, circuit cells designed for low power are described.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.4
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• pp.708-712
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• 1987

This paper deals with minimizing layout area of VLSI design. A long wire in a VLSI layout causes delay which can be reduced by using a driver. There can be significant area increase when many drivers are introduced in a layout. This paper describes a method to obtain tight bound on the worst-case increase in area when drivers are introduced along many long wires in a layout. The area occupied by minimum-area embedding for a circuit can depend on the aspect ratio of the bounding rectangle of the layout. This paper presents a separator-based area optimal embeddings for VLSI graphs in rectangles of several aspect ratios.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.29B no.8
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• pp.54-65
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• 1992

A huge amount of multiplications is required for 2-D filtering on the image data, making it difficult to implement a real-time quincuncial interpolator. In this paper, efficient design technique and VLSI structures for 2-D multipleierless filter are presented. In the filter design, by introducing an efficient scheme for discretizing the frequency response of the prototype filter, it is shown that a significant amount of the computational burden required in the conventional techniques, such as local search, branch and bound techniques, could be saved. In the case of 5$\times$5 filter, it is found that the design technique described in this paper could save about 80% of the computation time, compared to the conventional methods, while providing a comparable performance. For a hardware implementation, two different VLSI structures for 2-D multiplierless filter are also introduced in the paper : One is for block parallel processing and the other for scan-line parallel processing. In both structure, the AP(area-period) figure improves over Wu's structure[4].

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.5A
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• pp.702-708
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• 2000

In this paper, we designed one-dimensional VLSI array with optimal pipeline period for high speed processing fractal image compression. The algorithm is derived which is suitable for VLSI array from axed block partition algorithm. Also the algorithm satisfies high quality of image and high compression-ratio. The designed VLSI array has optimal pipeline relied because the required processing time of PEs is distributed as same as possible. As this result, we can improve the processing speed up to about 3 times. The number of input/output pins can be reduced by sharing the input/output and arithmetic unit of the domain blocks and the range blocks.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1085-1089
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• 1987

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.2 s.344
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• pp.96-104
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• 2006

This paper presents design methodology, encient verification and implementation of a CAN protocol controller. The design methodology uses a heuristic technique to make the design flexible and cost effective. Using the design methodology, we created architecture for a CAN controller which has flexible and low cost features. For faster time-to-market and reliable operation of the designed CAN protocol controller, we p개posed a three-step verification process which uses three different kinds of verification techniques. The goal of this three-step verification is to reduce the number of test sequences in order to rapidly implement the design without loss of reliability for faster time-to-market. The designed CAN protocol controller was fabricated using a 0.35 micrometer CMOS technology.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.1
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• pp.104-112
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• 1989

A design automation method for sequential circuits implementation by mans of PLA is discussed, and an optimal state-code assignment algorithm to minimize the PLA area is proposed. In order to design sequential circuit automatically, DASL (Design Automation Support Language) [8] which is easy to describe and powerful to synthesize, is proposed and used to describe sequential circuit, An optimal statecode assignment algorithm which considers next states and outputs simultaneously is proposed, and by adopting this algorithm to various examples, the area of PLA is reduced by 10% comparing privious methods. This system is constructed to design microinstruction, FSM, VLSI control part synthesis.