• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.292-301
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• 2001

IDDQ Testing is a very effective testing method to detect many kinds of physical defects occurred in CMOS VLSI circuits. In this paper, we consider the most commonly occurring bridging faults in current CMOS technologies and develop pattern generator for IDDQ testing using efficient IDDQ test algorithms. The complete set of bridging faults between every pair of all nodes(internal and external nodes) within circuit under test is assumed as target fault model. The merit of considering the complete bridging fault set is that layout information is not necessary. Implemented test pattern generator uses a new neighbor searching algorithm and fault collapsing schemes to achieve fast run time, high fault coverage, and compact test sets. Experimental results for ISCAS benchmark circuits demonstrate higher efficiency than those of previous methods.

• Journal of Korea Society of Industrial Information Systems
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• v.27 no.1
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• pp.27-35
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• 2022

In the most IPS (Indoor Positioning System), it is available to specify the user's movement by sending a specific signal from a tag such as a beacon to multiple receivers. This method is very efficiently used in places where the number of people is limited. On the other hand, in large commercial facilities, it is nearly difficult to apply the existing IPS method because it is necessary to attach a tag to each customer. In this paper, we propose a system that uses an external sensor grid to identify people's movement without using tags. Each sensor node uses both an ultrasonic sensor and an infrared sensor to monitor people's movements and sends collected data to the main server through wireless transmission for easy system maintenance. The operation was verified using the FPGA board, and we designed a VLSI circuit in 180nm process.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.1
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• pp.47-56
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• 1999

As the density of logic gates of VLSI chips has rapidly increased, more number of I/O pins has been required. This results in bigger package size and higher packager cost. The package cost is higher than the cost of bare chips for high I/O count VLSI chips. As the density of logic gates increases, the reduction method of the number of I/O pins for a given complexity of logic gates is required. In this paper, we propose the novel I/O interface circuit using CTR (Constant-Transition-Rate) code to reduce 50% of the number of I/O pins. The rising and falling edges of the symbol pulse of CTR codes contain 2-bit digital data, respectively. Since each symbol of the proposed CTR codes contains 4-bit digital data, the symbol rate can be reduced by the factor of 2 compared with the conventional I/O interface circuit. Also, the simultaneous switching noise(SSN) can be reduced because the transition rate is constant and the transition point of the symbols is widely distributed. The channel encoder is implemented only logic circuits and the circuit of the channel decoder is designed using the over-sampling method. The proper operation of the designed I/O interface circuit was verified using. HSPICE simulation with 0.6 m CMOS SPICE parameters. The simulation results indicate that the data transmission rate of the proposed circuit using 0.6 m CMOS technology is more than 200 Mbps/pin. We implemented the proposed circuit using Altera's FPGA and confimed the operation with the data transfer rate of 22.5 Mbps/pin.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.6
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• pp.85-96
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• 2000

It is necessary that fully differential operational amplifier circuit should drive an external load in the VLSI design such as SCF(Switched Capacitor Filter), D/A Converter, A/D Converter, Telecommunication Circuit and etc. The conventional CMOS operational amplifier circuit has many problems according to CMOS technique. Firstly, Capacity of large loads are not able to operate well. The problem can be solve to use class AB stages. But large loads are operate a difficult, because an element of existing CMOS has a quadratic functional relation with input and output voltage versus output current. Secondly, Whole circuit of dynamic range decrease, because a range of input and output voltages go down according as increasing of intergration rate drop supply voltage. The problem can be improved by employing fully differential operational amplifier using differential output stage with wide output swing. In this paper, we proposed new current mirror has large output impedance and good current matching with input an output current and compared with characteristics for operational amplifier using cascoded current mirror. To obtain large output swing and low power consumption we suggest a fully differential operational amplifier. The circuit employs an output stage composed new current mirror and two amplifier stage. The proposed circuit is layout and circuit of capability is inspected through simulation program(SPICE3f).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.12
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• pp.1970-1982
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• 1993

This paper describes an efficient array algorithm for parallel computation of vector-radix two-dimensional (2-D) fast discrete cosine transform (VR-FCT), and its VLSI implementation. By mapping the 2-D VR-FCT onto a 2-D array of processing elements (PEs), the butterfly structure of the VR-FCT can be efficiently importanted with high concurrency and local communication geometry. The proposed array algorithm features architectural modularity, regularity and locality, so that it is very suitable for VLSI realization. Also, no transposition memory is required, which is invitable in the conventional row-column decomposition approach. It has the time complexity of O(N+Nnzp-log2N) for (N*N) 2-D DCT, where Nnzd is the number of non-zero digits in canonic-signed digit(CSD) code, By adopting the CSD arithmetic in circuit desine, the number of addition is reduced by about 30%, as compared to the 2`s complement arithmetic. The computational accuracy analysis for finite wordlength processing is presented. From simulation result, it is estimated that (8*8) 2-D DCT (with Nnzp=4) can be computed in about 0.88 sec at 50 MHz clock frequency, resulting in the throughput rate of about 72 Mega pixels per second.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.695-698
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• 1998

Today SOC(system on a chip) is a trend in VLSI design society. Especially MML(merged memory Logic) process provides designers with good chances to implement SOC which is consists of DRAM, SRAM, Logic and A/D mixed mode ciruit blocks. Designers need good circuit library which is reliable and easy to tune for specific design. For this need we present semi-automated analog compiler methodology. And we aplied this design methodology to resistor-string DAC design.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.978-980
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• 1987

This paper presents a scheme of $16{\times}16$ VLSI crosspoint chip as a key Component in future broadband switching network operating at bit rates UP to 140Mbit/s using space division switching technique. First, functional requirements of the chip are investigated in terms of a large switching unit. Then, a regeneration circuit to provide reshaping of previsiously switched signals is presented.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1986.10a
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• pp.92-102
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• 1986

In this paper, Modular cell approach was applied to custom IC design or RS decoder. For the design of RS decoder by modular cells, 3 basic cells and one extra circuit are designed, these are, SYN cell for syndrome calculation, AL cell for error locator polynomial calculation, and REM cell for remaining error transform calculation. RS decoder design by these basic cells is very simple and regular, and naturally suitable for VLSI RS decoder design.

• 제어로봇시스템학회:학술대회논문집
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• 1995.10a
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• pp.69-70
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• 1995

This paper considers the applications of cellular automata in order to design self-organizing artificial neural decision systems such as self-organizing neurocomputer circuit, machines, and artifical life VLSI circuits for controlling mechanical systems. We consider the L-system and show the results of growth of plants in artificial life.

• ETRI Journal
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• v.23 no.3
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• pp.138-149
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• 2001

Due to the rapidly growing complexity of VLSI circuits, test methodologies based on delay testing become popular. However, most approaches cannot handle custom logic blocks which are described by logic functions rather than by circuit primitive elements. To overcome this problem, a new path delay test generation algorithm is developed for custom designs. The results using benchmark circuits and real designs prove the efficiency of the new algorithm. The new test generation algorithm can be applied to designs employing intellectual property (IP) circuits whose implementation details are either unknown or unavailable.