References
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- Proc. of Int’l Test Conf. Model for Delay Faults Based Upon Paths Smith, G.
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- IEEE Trans. on CAD no.Sept. On Delay Fault Testing in Logic Circuits Lin, C.
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- Proc. of Design Automation Conf. Robust Delay Fault Test Generation and Synthesis for Testability under a Standard Scan Design Methodology Cheng, K.;Devadas, S.;Keutzer, K.
- Proc. of Int’l Conf. on Computer Design Path Delay Fault Simulation for a Standard Scan Design Methodology Kang, S.;Underwood. B.;Law, W.
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