• The Journal of Korean Institute of Communications and Information Sciences
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• v.37A no.11
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• pp.993-1000
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• 2012

In this research, we proposed an efficient VLSI architecture of the lifting-based 2D DWT (Discrete Wavelet Transform) filter with 100% hardware utilization. The (9,7) filter structure has been applied and extendable to the filter length. We proposed a new block-based scheduling that computes the DWT for the lower levels on an "as-early-as-possible" basis, which means that the calculation for the lower level will start as soon as the data is ready. Since the proposed 2D DWT computes the outputs of all levels by one row-based scan, the intermediate results for other resolution levels should be kept in storage such as the Data Format Converter (DFC) and the Delay Control Unit (DCU) until they are used. When the size of input image is $N{\times}N$ and m is the filter length, the required storage for the proposed architecture is about 2mN. Since the proposed architecture processes the 2D DWT in horizontal and vertical directions at the same time with 4 input data, the total period for 2D DWT is $N^2(1-2^{-2J})/3$.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.12
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• pp.41-50
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• 1999

In this paper, the new VLSI architecture of a reconstruction filter for morphological image segmentation is proposed. The filter, based on the $h_{max}$ operation, simplifies the interior of each region while preserving the boundary information. The proposed architecture adopts a partitioned memory structure and an efficient image scanning strategy to reduce the operations. The proposed memory partitioning scheme makes it possible that every data required for processing can be read from each memory at a time, resulting in parallel data processing. By the extended connectivity consideration, the operation is much decreased because more simplification is achieved in scanning stage. The selective raster scan strategy endows the satisfactory noise removal capability with negligible hardware complexity increase. The proposed architecture is designed using VHDL, and functional evaluation is performed by the CAD tool, Mentor. The experiment results show that the proposed architecture can simplify image profile with less than 18% operations of the conventional method.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.678-681
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• 2002

In this paper, we propose a block LMS algorithm using distributed arithmetic (BDA) and a multi-memory block structured BDA (MBDA). Moreover, we propose an effective VLSI architecture of adaptive digital filter using MBDA, and evaluate the sampling rate and output latency.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.871-874
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• 1999

We propose a low complexity M-D(multidimensional) TCM decoder VLSI architecture for ADSL System. We use the shared subset decoder module by modifying the whole decoding procedure. We reduce power consumption by using the MSA (modulo set area) operation, which removes multiplication in 4D metric calculation. Also the proposed TCM decoder reduces chip area. It can be adopted in high-speed xDSL system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.11
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• pp.1502-1506
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• 2016

HEVC (High Efficiency Video Coding) is a recently proposed video compression standard that has a two times greater coding efficiency than previous video compression standards. The key factors of high compression performance and increasement of computational complexity are the various types of block partitions and modes of intra prediction in HEVC. This paper presents an intra prediction hardware architecture for HEVC utilizing pipelining and interleaving techniques to increase the efficiency and performance while reducing the requirement for hardware resources.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.679-682
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• 1998

This paper presents the VLSI implementation of RS(reed-solomon) decoder using the Modified Euclidean Algorithm(hereafter MEA) for DVD(Digital Versatile Disc) and CD(Compact Disc). The decoder has a capability of correcting 8-error or 16-erasure for DVD and 2-error or 4-erasure for CD. The technique of polynomial evaluation is introduced to realize syndrome calculation and a polynomial expansion circuit is developed to calculate the Forney syndrome polynomial and the erasure locator polynomial. Due to the property of our system with buffer memory, the MEA architecture can have a recursive structure which the number of basic operating cells can be reduced to one. We also proposed five criteria to determine an uncorrectable codeword in using the MEA. The overall architecture is a simple and regular and has a 4-stage pipelined structure.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.07a
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• pp.239-239
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• 2004

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.3
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• pp.137-144
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• 1990

We describe how single layer perceptrons and new nonsymmetry feedback type neural networks can be implemented by VLSI CMOS technology. The network described provides a flexible tool for evaluation of boolean expressions and arithmetic equations. About 50 CMOS VLSI chips with an architecture based on two neural networks have been designed and me being fabricated by 2-micrometer double metal design rules. These chips have been developed to study the potential of neural network models for the use in character recognition and for a neural compute.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.1
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• pp.42-46
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• 2010

Encapsulation for information security is often carried out in Galois field in the form of arithmetic operations. This paper proposes how to efficiently perform exponentiation of arithmetic information on Galois field. Especially, by improving an existing bit-parallel exponentiator to exclude elements with heavy gate counts and to take advantage of system constants, this paper proposes how to implement a VLSI architecture with high performance even for large m.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.54-64
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• 2010

Reed-Solomon (RS) codes are the most widely used error correcting codes in digital communications and data storage. Recently, Sudan found algorithm of list decoder for RS codes. List decoder has larger decoding radius than conventional hard-decision decoding algorithms and return more than one candidate polynomial. But, the algorithm includes interpolation and factorization step that demand massive computations. In this paper, an efficient architecture and processing schedule are proposed. The architecture consists of R-MAC, memories, and control unit. The R-MAC computes both of RC and PU steps that are main part of the factorization algorithm. The proposed architecture can achieve higher hardware utilization efficiency (HUE) and throughput by using efficient processing schedule and memory architecture. Also, the architecture can be designed flexibly with scalability for various applications. We design and synthesize our architecture using Dongbu-Anam $0.18{\mu}m$ standard cell library and the maximum clock frequency is 330MHz.