• Journal of KIISE:Computer Systems and Theory
• /
• v.29 no.12
• /
• pp.648-654
• /
• 2002

The Virtual Interface Architecture(VIA) is an industry standard for communication over system area networks(SANs). M-VIA is a software implementation of VIA technology on Linux. In this paper, we implemented the M-VIA on an AceNIC Gigabit Ethernet by developing a new AceNIC driver for the M-VIA. We analyzed the M-VIA data segmentation processes. When a Gigabit Ethernet MTU is larger than 1514 bytes, M-VIA data segmentation size leaves much room for improvement. So we experimented with various MTU and M-VIA data segmentation size and compared the performances.

• Journal of the Microelectronics and Packaging Society
• /
• v.13 no.4
• /
• pp.45-50
• /
• 2006

Copper via filling is the important factor in 3-D stacking interconnection of SiP (system in package). As the packaging density is getting higher, the size of via is getting smaller. When DC electroplating is applied, a defect-free hole cannot be obtained in a small size via hole. To prevent the defects in holes, pulse and pulse reverse current was applied in copper via filling. The holes, $20\and\;50{\mu}m$ in diameter and $100{\sim}190\;{\mu}m$ in height. The holes were prepared by DRIE method. Ta was sputtered for copper diffusion barrier followed by copper seed layer IMP sputtering. Via specimen were filled by DC, pulse and pulse-reverse current electroplating methods. The effects of additives and current types on copper deposits were investigated. Vertical and horizontal cross section of via were observed by SEM to find the defects in via. When pulse-reverse electroplating method was used, defect free via were successfully obtained.

• Journal of the Microelectronics and Packaging Society
• /
• v.14 no.3
• /
• pp.37-42
• /
• 2007

Copper deposition studies have been actively studied since interests on 3D SiP were increased. The defects inside via can be easily formed due to the current density differences on entrance, bottom and wall of via. So far many different additives and current types were discussed and optimized to obtain void-free copper via filling. In this research acid cupric sulfate plating bath containing additives such as PEG, SPS, JGB, PEI and wave current applied electroplating were examined. The size and shape of grain were influenced by the types of organic additives. The cross section of specimen were analyzed by FESEM. When PEI was added, the denser copper deposits were obtained. Electroplaing time was reduced when 2 step via filling was employed.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2009.10a
• /
• pp.258-261
• /
• 2009

In this work we present a process to fabricate lowtemperature polysilicon (LTPS) TFTs on polyimide (PI) layers, spin-coated on Si-wafer used as rigid carrier. This process has been then used to fabricate elementary circuits as well as circuits for sensor applications.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2002.11a
• /
• pp.509-512
• /
• 2002

VIA 는 클러스터 또는 시스템 영역 네트워크를 위한 표준화된 사용자수준 통신 아키텍쳐이고, GNBD 는 LINUX 클러스터에서 IP 네트워크 설비를 기반으로 GFS 공유 파일 시스템을 설치할 때 사용하는 네트워크 블록 디바이스이다. GNBD 는 TCP/IP 상의 소켓을 기반으로 구현되어 있기 때문에, VIA 를 사용하는 클러스터이더라도 VIA 하드웨어 상에서 TCP/IP 소켓을 통하여 GNBD 를 작동시킨다. VIA 와 같이 물리적 연결이 신뢰성이 높고 높은 수준의 기능을 제공하는 경우는 같은 클러스터 안에서 TCP/IP 프로토콜 스택을 사용할 필요가 없다. 그래서 우리는 VIA 를 이용하지만 TCP/IP를 사용하지 않는 GNBD/VIA를 구현하였고, 동일한 VIA 하드웨어를 사용하면서 TCP/IP 모듈을 이용하는 GNBD 보다 파일시스템의 읽기(쓰기) 성능이 약 20%(30%) 향상된다는 것을 확인하였다. 본 논문에서는 VIA상에서 동작하는 GNBD/VIA의 성능 측정값과 그 위에 설치된 파일시스템의 을 보여주고, 그 결과를 상세히 분석하여 GNBD/VIA 상에 설치된 파일 시스템이 발휘할 수 있는 성능의 한계를 제시한다. 제시하는 한계치는 GNBD/VIA 뿐만 아니라 TCP/IP 상의 소켓을 사용하는 GNBD에도 적용할 수 있다.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.45 no.8
• /
• pp.8-14
• /
• 2008

In this paper, the effects of ground size on the characteristics such as input resistance, fractional bandwidth, and radiation efficiency of epsilon negative (ENG) zeroth order resonance (ZOR) antennas were investigated theoratically. Two types of ENG ZOR antennas were studied: mushroom ENG ZOR antenna with via and via-free defected ground structure (DGS) ENG ZOR antenna. It was confirmed that the ground size had more effects on the characteristics of a Via-free ZOR antenna than those of mushroom ZOR antenna with via. The via-free antenna could radiate properly with the required size of ground plane since the size of ground plane should exceed some critical value for DGS to suitably operate. As a height of substrate of mushroom ZOR antenna with via increased, the fractional bandwidth and radiation efficiency were improved. On the other hand, as a height of via-free ZOR antenna increased, the fractional bandwidth and radiation efficiency were degraded. Finally, a via-free ZOR antenna had an advantage of compactness even though its fractional bandwidth is narrow and its radiation efficiency is poor, compared with thoses of mushroom ZOR antenna with via.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2006.11a
• /
• pp.233-234
• /
• 2006

In this paper, Via hole pore were investigated during PLAS (PessureLess Assisted Constrained Sintering) process of LTCC. Ag and Ag-Pd paste mixture were tested for via paste. Ag paste with 10~25% Ag-Pd paste showed no via hole pore, but further increase of Ag-Pd contents in via paste increased via pore. From shrinkage curve, 10~25% Ag-Pd paste showed expansion behaviors before shrink and this phenomena result in the reduction of via hole pore during PLAS process.

• Proceedings of the Korean Institute of Surface Engineering Conference
• /
• 2009.10a
• /
• pp.171-172
• /
• 2009

TSV(through via silicon)를 이용한 Via의 Cu 충전에서 Seed 층의 역할은 전류의 흐름을 가능하게 하는 중요한 역할을 하고 있다. Via에 각각 Ti/Au, Ti/Cu를 증착한 후 Ti/Cu가 Ti/Au를 대체 할 수 있는지를 알아보기 위해 먼저 실리콘 웨이퍼에 via를 형성하고, 형성된 via에 기능성 박막층으로 절연층(SiO2) 및 시드층을 형성하였다. 전해도금을 이용하여 Cu를 충전한 결과 Ti/Au 및 Ti/Cu를 증착한 두 시편 모두 via와 seed층 접합면에 박리 등의 결함이 없었고, via 내부 또한 void나 seam 등이 관찰되지 않고 우수하게 충전된 것을 확인할 수 있었다.

• Proceedings of the IEEK Conference
• /
• 2008.06a
• /
• pp.557-558
• /
• 2008

This paper presents the effects of via losses to be connected with an embedded DPDT(Double Pole Double Thru) in a substrate. The substrate consists of two ABF(Ajinomoto Bonding Film) and a Epoxy core. In order to verify and test effects of via, via chains in a substrate using SoP-L process are proposed and measured. Via loss can be calculated as averaging the total via holes. The exact loss of a DPDT switch embedded in substrate are extracted by using the results of via chain and measured data from embedded DPDT. The calculated one via insertion loss is about 0.0005 dB on basis of measured via chains. This result confirms very low loss in via. So the inserti on loss of the embedded switch is confirmed only switch loss as loss is 0.4 dB.

• Journal of the Microelectronics and Packaging Society
• /
• v.15 no.1
• /
• pp.45-50
• /
• 2008

The effects of electrolytes and additives on the electropolishing of 50 and $20{\mu}m$ diameter copper via were investigated to flatten 3D SiP through via. The termination time was determined with analysis of applied potential on anode and cathode to avoid excess electropolishing. Acetic acid played a role of accelerator and glycerol played a role of inhibitor in phosphoric acid electrolytes. The overplated copper on the through via was effectively electropolished in the phosphoric electrolytes with acetic acid and glycerol addition. The electropolishing was terminated at the point of abrupt change of applied potential to remove only overplated copper on the through via.