• Journal of the Korean Institute of Intelligent Systems
• /
• v.8 no.5
• /
• pp.83-97
• /
• 1998

This paper developes an integrated environment CAD system that can design and implement an accurate and cost-effective FLC automatically. For doing this, an integrated development environment (IDE) (called FADIS; FLC Automatic Design and Implementation Station) is built by the seemless coupling of many existing. CAD tools in an attempt to the FADIS performs various functions such that (1) i~utomatically generate the VHDL components appropriate for the proposed FLC architecture from the various design parameters (2) simulate the generated VHDL code on the Synopsys's VHDL Simulator, (3) automatically compiler, (4) generate the optimized, placed, and routed rawbit files from the synthesized modules by Xilinx's XactStep 6.0, (5) translate the rawbit files into the downloadable ex- [:cution reconfigurable FPGA board (VCC's EVCI), and (7) continuously monitor the control status graphically by communicating the FLC with the controlled target via S-bus. The developed FADIS is tested for its validity by carrying out the overall procedures of designing and implementing the FLC required for the truck-backer upper control, the reduction of control execution time due to the controller's FPGA implementation is verified by comparing with other implementations.

• Electronics and Telecommunications Trends
• /
• v.4 no.3
• /
• pp.121-132
• /
• 1989

최근에 시스팀을 설계하는데 있어서, 디지틀 기기를 구성하는 전자부품과 Sub-system 또는 시스팀 전체에 대하여 하나의 표준언어 체계로 기술할 수 있는 VHDL의 발전과정 및 기술동향에 대해 살펴보고 이들 중 현재 부각되고 있는 것들에 대하여 요약하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2002.11a
• /
• pp.727-730
• /
• 2002

최근 키를 가지고 다니는 불편함과 보안성을 고려한 전자 키들이 많이 생산되고 있다. 키의 불편함과 보안성을 보완하는 방법에는 비밀번호 입력, 지문인식, 홍체인식 등의 방법이 이용되고 있는데, 본 논문에서는 비밀번호를 입력하는 방법으로 설계하였다. Altera사의 Software인 MAXPLUS II를 이용하여 설계하였고, Hardware Language인 VHDL을 이용하였다.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.24 no.9A
• /
• pp.1442-1450
• /
• 1999

In this paper, we present an efficient hardware architecture for the frame memory of the MPEG-2 video encoder. Both the total size of internal buffers and the number of logic gates are reduced by the proposed memory map which can provide an effective interface between MPEG-2 video encoder and the external DRAM. Furthermore, the proposed scheme can reduce the DRAM access time. To realize the frame memory hardware,$0.5\mu\textrm{m}$, VTI, vemn5a3 standard cell library is used. VHDL simulator and logic synthesis tool are used for hardware design and RTL (register transfer level) function verification. The frame memory hardware emulator of the proposed architecture is designed for gate-level function verification. It is expected that the proposed frame memory hardware using VHDL can achieve suitable performance for MPEG-2 MP@ML.

• Journal of Satellite, Information and Communications
• /
• v.9 no.2
• /
• pp.45-51
• /
• 2014

Luby transform (LT) codes are a class of ratelss codes, and they have capability of generating infinite length of parities with a given information length. These rateless codes can be effectively utilized to provide broadcasting and multicasting services where each user is in a different channel condition. For this reason, there have been a number of researches on the application of rateless codes for satellite systems. In this paper, by considering the current research status on rateless codes, we present VHLD implementation results of LT codes, for future hardware implementation for satellite systems. The results demonstrated in this paper can be utilized as a basic information on efficient utilization of rateless codes in the future satellite systems.

• The Transactions of the Korea Information Processing Society
• /
• v.3 no.5
• /
• pp.1346-1353
• /
• 1996

In this paper, we propose a modeling method for the flip-flops and test generation algorithms to detect the faults in the sequential circuits using VHDL in the high-level design environment. RS, JK, D and T flip-flops are modeled using data flow types. The sequence of micro-operation which is the basic structure of a chip-level leads to a control point where varnishing occurs to one of two micro- operation sequence. In order to model the fault of one micro-operation(FMOP) that perturb another micro-operation effectively, the concept of goal trees and some heuristic rules are used. Given a faulty FMOP or fault of control point (FCON), a test pattern is generated by fault sensitization, path sensitization and determination of the imput combinations that will justify the path sensitization. The fault models are restricted to the data flow model in the ARCHITECTURE statement of VHDL. The proposed algorithm is implemented in the C language and its efficiency is confirmed by some examples.

• Journal of KIISE:Computing Practices and Letters
• /
• v.11 no.1
• /
• pp.26-35
• /
• 2005

Generally, we employ FSMs for the design of controllers in digital systems. FSMs are Implemented with state diagrams generated from control flow. With HDL, we design and verify FSMs based on state diagrams. As the number of states in the system increases, the verification or modification processes become complicated, error prone and time consuming. In this paper, we propose a control flow oriented hardware description language at the register transfer level called Cycle-C. Cycle-C describes FSMs with timing information and control How intensive algorithms. The Cycle-C description is automatically converted into FSMs in the form of synthesizable RTL VHDL. In experiments, we design FSMs for control intensive interface circuits. There is little area difference between Cycle-C design and manual design. In addition, Cycle-C design needs only 10~50% of the number lines of manual RTL VHDL designs.

• Journal of Digital Contents Society
• /
• v.7 no.3
• /
• pp.147-151
• /
• 2006

In recent years, the Internation Standard ISO/IEC 18000-6 is announced and a new scheme of Type C is added to conventional standard. Among the RFID systems the ISO/IEC 18000-6 standard is the most interesting to companies due to its potential market growth. The operating frequency is between 860-960 MHz, and three kinds of RFID system are included in the standard, i.e. type A, B and C. In this paper, we implemented the data frame of type C with baseband coding using VHDL. The data frame is encoded based on Miller code and FM0. We showed the implementation results with waveforms. The data frame was proved that it is properly implemented by the experiment of transmission and receiving operation.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.10 no.7
• /
• pp.1165-1171
• /
• 2006

In this paper, we designed radio data transceiver to control the machine or equipments for automation in local areas. The designed module can transmit data with 153.6Kbps and uses 424MHz RF carrier to transmit data in the ISM band regulation. It has a processor, CPLD chip of the Altera Company, to control the data in transmitting and receiving. The processor is implemented by programming with VHDL. We will make this module with compact in dimension and higher data rate and apply to RFID technology.

• Proceedings of the IEEK Conference
• /
• 2004.08c
• /
• pp.463-467
• /
• 2004

A FTS (Flight Termination System) is a system that resides in a flying object such as a rocket, unmanned airplane, helicopter, missile, etc., receives commands from ground stations or detects coordinates automatically, and accomplishes a destruction command in case the object does not follow the presumed orbit. In this paper, we address the implementation of a communication modem for the FTS modem. We present general theory, simulation results using Matlab, and several results on the implementation using VHDL.