• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1013-1016
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• 1998

A method for generation of design verification tests from behavior-level VHDL program is presented. Behavioral VHDL programs contain multiple communicating processes, signal assignment statements. So for large, complex system, it is difficult problem to test or simulation. In this paper, we proposed a new hardware design verification method. For this method generates control flow graph(CFG.) and process modeling graph(PMG) in the given under the testing VHDL program. And this method proved very effective that all the assumed design errors could be detected.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.819-822
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• 2003

This paper defines an algorithmic description language in cycle-accurate level which can be used to design hardware components. The proposed language is less complex and more flexible than VHDL language. In that the language includes C-like control flow descriptions and brief timing information(i.e. clock cycle boundaries) indicated by 'wait_edge' statements. We generate RTL VHDL codes from the descriptions. The proposed language requires only 10～30% of the # of lines to describe the same functionality compared with RTL VHDL.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.3
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• pp.185-197
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• 2001

Recently, the design method by VHDL coding and synthesis has been used widely. As the integration ratio increases, the amount design by VHDL at a time also increases so many coding errors occur in a design. Thus, lots of time and effort is dissipated to detect those coding errors. This paper proposed a method to verify the coding errors in VHDL behavioral-level designs. As the methodology, we chose the method to detect the coding error by applying the generated set of verifying patterns and comparing the responses from the error-free case(gold unit) and the real design. Thus, we proposed an algorithm to generate the verifying pattern set for the coding errors. Verifying pattern generation is peformed for each code and the coding errors are classified as two kind: condition errors and assignment errors. To generate the patterns, VHDL design is first converted into the corresponding CDFG(Control & Data Flow Graph) and the necessary information is extracted by searching the paths in CDFG. Path searching method consists of forward searching and backward searching from the site where it is assumed that coding error occurred. The proposed algorithm was implemented with C-language. We have applied the proposed algorithm to several example VHDL behavioral-level designs. From the results, all the patterns for all the considered coding errors in each design could be generated and all the coding errors were detectable. For the time to generate the verifying patterns, all the considered designed took less than 1 ［sec］ of CPU time in Pentium-II 400MHz environments. Consequently, the verification method proposed in this paper is expected to reduce the time and effort to verify the VHDL behavioral-level designs very much.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.3C
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• pp.64-68
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• 2005

Reed-Solomon code is one of the most versatile channel codes. The encoder can be implemented with two famous structures: ordinary and bit-serial. The ordinary encoder is generally known to be complex and fast, while the bit-serial encoder is simple and not so fast. However, it may not be true for a longer codeword length at least in VHDL implementation. In this letter, it is shown that, when the encoder is implemented with VHDL, the number of logic gates of the bit-serial encoder might be larger than that of the ordinary encoder if the dual basis conversion table has to be used. It is also shown that the encoding speeds of the two VHDL implemented encoders are exactly same.

• Journal of the Korea Computer Industry Society
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• v.9 no.4
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• pp.157-170
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• 2008

In this paper, we described the Parwan(PAR-1) CPU that be developed as a reduced processor at Messachusetts Microelectronics Center using a VHDL at the behavioral level and then described by connecting CPU components at the dataflow level. Finally, we used Test-bench method to simulate and verify execution of CPU processor that was designed using a VHDL <중략> Here, Presented method was to enable information exchange of design and representation of operation were very exact and simple. Also, a documentation of design was available and it was easy that verify a operation of designed processor. The behavioral description of VHDL aids designer as we verify our understanding of the designed system, thus the dataflow description can be used to verify the bussing and register structure of the design.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.3
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• pp.31-31
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• 2001

최근 VHDL 코딩 및 합성방법에 의한 설계가 널리 사용되고 있다. 집적도가 증가함에 따라 VHDL에 의한 설계 또한 그 분량이 증가하여 많은 코딩오류가 발생하고 있으며, 이를 검색하는데 많은 시간과 노력이 소요되고 있다. 본 논문에서는 VHDL 행위-레벨 설계를 대상으로 코딩오류를 검색하는 방법을 제안하였다. 그 방법에 있어서는 검색패턴을 생성하여 오류가 없는 응답과 설계의 응답을 비교함으로써 설계오류를 찾는 방법을 택하였다. 따라서 본 논문에서는 코딩오류를 검색하기 위한 검색패턴을 생성하는 알고리듬을 제안하였다. 검색패턴 생성은 각 코드에 대해 수행하며, 할당오류와 조건오류를 구분하여 수행하였다. 패턴생성을 위해 VHDL 코드를 CDFG로 변환하여 사용하며, CDFG상의 경로를 탐색하여 패턴생성에 필요한 정보를 추출한다. 경로탐색은 오류가 발생하였다고 가정한 지점으로부터 역방향 탐색과 정방향 탐색을 수행하여 패턴을 생성한다. 제안한 알고리듬은 C-언어로 구현하였다. 펜티엄-Ⅱ 400MHz의 환경에서 여러 가지 VHDL 행위-레벨 설계를 대상으로 제안한 알고리듬을 적용하였다. 그 결과, 고려한 모든 설계의 모든 코드에 대한 검색패턴을 생성할 수 있었으며, 가정한 모든 오류를 검색할 수 있었다. 검색패턴 생성에 소요되는 시간은 고려한 모든 대상 설계에서 1초 미만의 CPU 시간을 보여 속도면에서도 매우 우수함을 나타내었다. 따라서 본 논문에서 제안한 검색방법은 VHDL에 의한 설계에서 설계검증에 필요한 시간과 노력을 상당히 감소시킬 것으로 기대된다.

• Proceedings of the Korea Society for Simulation Conference
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• 2001.05a
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• pp.82-87
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• 2001

In this paper we described the generation method of interface logic which can be replace between IP and IP handshaking signal with asynchronous logic circuit. Especially, we suggest the new \"Waveform Conversion Algorithm : Wave2VHDL\", if only mixed asynchronous timing waveform suggested which level type input and pulse type input for handshaking, we can convert waveform to flowchart and then replaced with VHDL code according to converted flowchart. Also, we assure that asynchronous electronic circuits for IP interface are generated by applying extracted VHDL source code from suggested algorithm to conventional domestic/abroad CAD Tool, and then we proved that coincidence simulation result and suggested timing diagram.g diagram.

• Proceedings of the KIEE Conference
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• 2002.11d
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• pp.197-199
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• 2002

The invention of VHDL(Very High Speed Integrated Circuit Hardware Description Language), Technical language of Hardware, is a kind of turning point in digital circuit designing, which is being more and more complicated and integrated. Because of its excellency in expression ability of hardware, VHDL is not only used in designing Hardware but also in simulation for verification, and in exchange and conservation, composition of the data of designs, and in many other ways. Especially, It is very important that VHDL is a Technical language of Hardware standardized by IEEE, intenational body with an authority. The biggest problem in modern circuit designing can be pointed out in two way. One is a problem how to process the rapidly being complicated circuit complexity. The other is minimizing the period of designing and manufacturing to survive in a cutthroat competition. To promote the use of VHDL, more than a simple use of simulation by VHDL, it is requested to use VHDL in composing logical circuit with chip manufacturing. And, by developing the quality of designing technique, it can contribute for development in domestic industry related to ASIC designing. In this paper in designing SMPS(Switching mode power supply), programming PWM by VHDL, it can print static voltage by the variable load, connect computer to chip with byteblaster, and download in Max(EPM7064SLCS4 - 5)chip of ALTER. To achieve this, it is supposed to use VHDL in modeling, simulating, compositing logic and product of the FPGA chip. Despite its limit in size and operating speed caused by the specific property of FPGA chip, it can be said that this method should be introduced more aggressively because of its prompt realization after designing.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.526-529
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• 2003

This paper presents two strategies to refute clock cycles when using stopping rule in VHDL model verification. The first method is that a semi-random variable is defined and the data that stay in the range of semi-random variable are skipped when stopping rule is running. The second one is to keep the old values of parameters when phases are changed. 12 VHDL models are examined to observe the effectiveness of strategies.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.7
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• pp.966-973
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• 1995

In this paper, we compare several methods for implementing a VHDL design database through a case study on VHDL tool development system. We implemented three versions of the VHDL design database which the VHDL tool development system is based on. The first version was coded in the C programming language following value-oriented paradigm. The second one was coded in the C++ programming language following object-oriented paradigm. The third one was implemented using an existing object-oriented database. Based on our experience, we present quantitatively the pros and cons of each implementation method. The value-oriented version was most difficult to implement but showed good performance. Compared to the value- oriented version, the C++ version was twice as easy to implement and showed about the same performance. Using an existing object-oriented database allowed easiest implementation but resulted in a 1.5 to 6 times slower version.