• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.1
• /
• pp.69-78
• /
• 2001

This paper presents the design and FPGA implementation of a FLEX PSP(Protocol Signal Processor) for the portable high speed paging system. In this approach, two algorithms are newly proposed for implementing the PSP which provides capabilities of the maximum 6,400bps at speed, high-channel throughput, real time error correction and an effective frame search function. One is an accurate symbol synchronization algorithm which is applied for synchronizing the interleaved 4-level bit symbols which are received at input stage of A/D converter, and the other is a modified fast decoding algorithm which is provided for realizing double error correction of (31,21)BCH signal. The PSP is composed of six functional modules, and each module is modelled in VHDL(VHSIC Hardware Description Language). Both functional simulation and logic synthesis have performed for the proposed PSP through the use of Synopsys$^{TM}$ tools on a Axil-320 Workstation, and where Altera 10K libraries are used for logic synthesis. From logic synthesis, we can see that the number of gates is about 2,631. For FPGA implementation, timing simulation is performed by using Altera MAX+ PLUS II, and its results will be also given. The PSP which is implemented in 6 FPGA devices on a PCB has been verified by means of Logic Analyzer.r.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.6
• /
• pp.431-441
• /
• 2003

This paper presents the design of 32 bit microprocessor for a sequence control using a field programmable gate array(FPGA). The microprocessor was designed by a VHDL with top down method, the program memory was separated from the data memory for high speed execution of sequence instructions. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 32 bits. And the real time debug operation was implemented for easeful debugging the designed processor with a single step run, PC break point run, data memory break point run. Also in this designed microprocessor, pulse instructions, step controllers, master controllers, BM and BCD type arithmetic instructions, barrel shift instructions were implemented for sequence logic control. The FPGA was synthesized under a Xilinx's Foundation 4.2i Project Manager using a V600EHQ240 which contains 600,000 gates. Finally simulation and experiment were successfully performed respectively. For showing good performance, the designed microprocessor for the sequence logic control was compared with the H8S/2148 microprocessor which contained many bit instructions for sequence logic control. The designed processor for the sequence logic showed good performance.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.32 no.4A
• /
• pp.325-329
• /
• 2007

In this paper, the modem based on EIA-709.2-A PL of powerline communication techniques which are considered to be important technologies for in-home control network systems was implemented via VHDL. In order to have the robust properties against existing noises over powerline channels, the information data using eight symbols was transmitted by transmitter and the receiver is composed of matched filter, averager, decision and detection parts in order to detect the right data from the received signals. The implemented PLC transceiver was downloaded into Altera's EP1S25C672 FPGA and the operation was verified successfully.

• Journal of the Institute of Convergence Signal Processing
• /
• v.2 no.4
• /
• pp.71-76
• /
• 2001

In this paper we propose the Digital Automatic Gain Controller for IEEE 802.11a-High-speed Physical Layer in the 5 GHz Band. The input gain it estimated by calculating the energy of the training symbol that it a synchronizing signal. The renewal gain is calculated by comparing the estimated gain with the ideal gain. The renewal gain is converted into the controlled voltage for GCA to reduce or amplify the input signals. We used a piecewise-linear approximation to reduce the hardware size. The gain control is performed seven times to provide more accurate gain control. The proposed automatic gain controller is designed with VHDL and verified by using the Xilinx FPGA.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.10 no.11
• /
• pp.2020-2025
• /
• 2006

H.264/AVC is newest video coding standard of the ITU-T Video coding Experts Group and the ISO/IEC Moving Picture Expets Group. Recently H.264/AVC has been adopted as a video compression standard in DMB and multimedia equipments. In this paper, we propose a H.264/AVC intra frame decoder which can minimize the memory usage and chip size. The proposed intra frame decoder is described in VHDL language and simulated in model_sim. It was verified in chip level by downloading to XCV1000E FPGA chip.

• Proceedings of the IEEK Conference
• /
• 2003.07e
• /
• pp.1787-1790
• /
• 2003

In this paper. we proposed a hardware(H/W) structure which can compress the video and embed the watermark in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into H/W with the efficient structure for FPGA. The global operations of the designed H/W consists of the image compression with the watermarking and the reconstruction, and the watermarking operation is concurrently operated with the image compression. The implemented H/W used the 59％(12943) LAB(Logic Array Block) and 9％(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70㎒ clock frequency over. So we verified the real time operation, 60 fields/sec(30 frames/sec).

• Proceedings of the KIEE Conference
• /
• 2003.07d
• /
• pp.2112-2114
• /
• 2003

In this paper, We used FPGA which was high speed counter implementation. It was Counting accurately rather fast so that there were we as a counter facility of the pulse implemented. We constructed wide environment rather because we used H8/3672 with FPGA. This FPGA was sythesized by A54SX72A. FPGA programmed by VHDL for a 208pin PQFP package. The measurement the pulse is possible though it peels off a maximum 200kHz. There is used at a stopping action movement and control of the body.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.25 no.5B
• /
• pp.966-973
• /
• 2000

In this paper, we propose a novel RS decoder design yielding smallr circuit size shorter coding latency. The proposed architecture of RS decoder has the following two features. First, circuit size reduced by using Euclid algorithm with mutual operation between cells. Second, coding latency is reduced by using higher frequency than syndrome and error value calculation block. We performed simulation with C language and MATLAB in order to verify the decoding algorithm and implemented using FPGA chips in VHDL.

• Proceedings of the Korea Information Assurance Society Conference
• /
• 2004.05a
• /
• pp.59-64
• /
• 2004

In this paper a design and an implementation of a crypto chip which implements SEED and Triple-DES algorithms are described. We designed it by VHDL(VHSIC Hardware Description Language) which is a designed system-description language. To apply the chip to various application, four operating Modes such as ECB, CBC, CFB, and CFB are supported. The chip was designed by the Virtex-E XCV2000E BG560 of Xilinx and we confirmed result of it at the FPGA implementation by functional and timing simulation using the Xilinx Foundation Series 3.li.

• Journal of the Korea Computer Industry Society
• /
• v.2 no.9
• /
• pp.1183-1190
• /
• 2001

In this paper, it used a different pipeline method from conventional method which is encoding the video signal of analog with digital. It designed with pipeline structure of 4 phases as the pixel clock ratio of the whole operation of the encoder, and secured the stable operational timing of the each sub-blocks, it was visible the effect which reduces a gate possibility as designing by the ROM table or the shift and adder method which is not used a multiplication flag method of case existing of multiplication of the fixed coefficient. The designed encoder shared with the each sub-block and it designed the FPGA using MAX+PLUS2 with VHDL.