• Journal of KIISE
• /
• v.43 no.5
• /
• pp.569-578
• /
• 2016

The PLC (Programmable Logic Controller) has been widely used for the development of digital control system of nuclear power plant. The PLC has high maintenance costs and increasing complexity, hence, FPGA (Field Programmable Gate Array) based digital control system has been considered as an alternative. However, the development of FPGA based digital control system is a challenge for PLC engineers because they are required to learn about new language to develop FPGA and knowledge and know-how acquired in the development of PLC is not transferable. In this study, we proposed and implemented an automatic translation tool for translation of FBD (Function Block Diagram), a programming language of PLC software, into VHDL (VHSIC Hardware Description Language). Automatically translating the FBD to VHDL using this tool allows PLC engineers to develop FPGA without any knowledge of the hardware description language.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.5
• /
• pp.180-187
• /
• 1996

This paper describes a post-layout simulation method using VHDL and C for verifying the architecture of antifuse-based FPGAs and the dedicated CAD system. An antifuse-based FPGA consists of programming circuitry including decoding logic, logic modules, segmented tracks, antifuses and I/O pads. The VHDL model which includes all these elements is used for logic verification and programming verification of the implemented circuit by reconstructing the logic circuit from the bit-stream generated from layout tool. The implemented circuit comprises of logic modules and routing networks. Since the routing delay of the complex networks is comparable to the delay of the logic module in the FPGA, the accurate post-layout simulation is essential to the FPGA system. In this paper, the C program calculates the delay of the routing netowrks using SPICE, elmore or horowitz delay models and the results feedback to the VHDL simulation. Critical path anc be found from this post-layout simulation results.

• Proceedings of the Korea Institute of Convergence Signal Processing
• /
• 2003.06a
• /
• pp.300-303
• /
• 2003

In this paper, a baseband module of the spread spectrum system with FPGA is designed. A spread spectrum system spreads the signal bandwidth necessary for information transmission. We focused on the design of FEC decoder, especially the convolutional code fo constraint length K=3, rate R=l/2, is designed. For the VHDL design the Xilinx Foundation 3.1 is used. As results, a spread spectrum modem with convolutional coding is designed and we have plan to apply this modem to short distances wireless communication.

• Journal of the Semiconductor & Display Technology
• /
• v.13 no.4
• /
• pp.71-76
• /
• 2014

This paper presents the implementation for the BLDC motor speed control system using VHDL and FPGA. The BLDC motor is widely used in automation for its good robustness and easy controllability. In order to control the speed of the BLDC motor, the PI controller used for static RPM output of the BLDC motor to variations in load. In addition, by using the DA converter, we were able to monitor the BLDC motor reference speed and the current speed through real time. The motor speed command and the parameters of the PI speed controller were modified easily by the FPGA and the AD converter. Finally, in order to show the feasibility of the control algorithm the speed control characteristics of the motor was monitored using an oscilloscope and the DA converter. Further, the speed control system was designed in this paper has shown the applicability of the drive system of the factory automation.

• Journal of KIISE:Computing Practices and Letters
• /
• v.8 no.6
• /
• pp.717-726
• /
• 2002

In this study, we analyze hardware implementation schemes of the ARS(Advanced Encryption Standard-128) algorithm that has recently been selected as the standard cypher algorithm by NIST(National Institute of Standards and Technology) . The implementation schemes include the basic architecture, loop unrolling, inner-round pipelining, outer-round pipelining and resource sharing of the S-box. We used MaxPlus2 9.64 for VHDL design and simulations and FLEX10KE-family FPGAs produced by Altera Corp. for implementations. According to the results, the four-stage inner-round pipelining scheme shows the best performance vs. cost ratio, whereas the loop unrolling scheme shows the worst.

• Proceedings of the KAIS Fall Conference
• /
• 2003.06a
• /
• pp.250-252
• /
• 2003

본 논문에서는 콘벌루션 부호를 사용한 대역확산 방식의 디지틀 통신모뎀을 FPGA를 이용하여 설계 및 검증을 하였다. 대역확산 방식에서의 콘벌루tus부호기(K=3, R=1/2), PN code(128chip) generator와 비터비 디코더를 Xilinx사의 FPGA 디자인 툴인 Xilinx Foundations3.1을 사용하여 VHDL simulation과 timing simulation을 수행하였고, FPGA 회로설계 검증 장비인 EDA-Lab 3000 장비를 사용하여 Xilinx사의 SPARTAN2 2S100PQ208칩에 configuration 한 후 Agilent사의 1681A logic analyzer를 사용하여 설계된 회로의 동작을 검증하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2002.11a
• /
• pp.727-730
• /
• 2002

최근 키를 가지고 다니는 불편함과 보안성을 고려한 전자 키들이 많이 생산되고 있다. 키의 불편함과 보안성을 보완하는 방법에는 비밀번호 입력, 지문인식, 홍체인식 등의 방법이 이용되고 있는데, 본 논문에서는 비밀번호를 입력하는 방법으로 설계하였다. Altera사의 Software인 MAXPLUS II를 이용하여 설계하였고, Hardware Language인 VHDL을 이용하였다.

• Journal of the Semiconductor & Display Technology
• /
• v.12 no.4
• /
• pp.27-32
• /
• 2013

In this paper, the boost converter was implemented by digital control in many applications of the step-up. The PWM(pulse width modulation) control module of boost converter was digitized at power converter using the FPGA device and VHDL. The boost converter was designed to output a fixed voltage through the PI control algorithm of the PWM control module even if input voltage and output load are variable. The boost converter was digitized can be simplified by reducing the size of the module and the external control components. Thus, the digital power IC has advantageous for weight reduction and miniaturization of electronic products because it can be controlled remotely by setting the desired output voltage and PWM control module. The boost converter using the digital power IC was confirmed through experiments and the good performances were showed from experiment results.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.46 no.6
• /
• pp.66-77
• /
• 2009

In this paper, we propose a CORBA middleware extension which is suitable to SCA based communication environment. The extensions guarantee the components to interconnect others without consideration about its implementation way and enables the developers to easily achieve the performance improvements in comparison to the existing methodology. This extension includes the HAO, the IDL2VHDL compiler, and the improvement of ORBit. The HAO is ORB implemented in logic level and is limited the some function according to the characteristic of FPGA. In addition, the IDL2VHDL compiler provides the mapping from CORBA IDL to VHDL, the VHSIC hardware description language, and the additional procedures for processing the component. Finally, the improved ORBit, CORBA ORB on GPP, can be direct connecting with the HAO on FPGA.

• Proceedings of the Korean Institute of Intelligent Systems Conference
• /
• 1997.11a
• /
• pp.67-72
• /
• 1997

본 논문은 저비용이면서 정확한 제어를 수행하는 새로운 퍼지 제어기의 재구성 가능한 FPGA 시스템상의 구현을 다룬다. 제안한 퍼지 제어기 (Fuzzy Logic Controller : FLC)의 시스템 구조와 이의 VHDL 설계 및 시뮬레이션은 다른 논문에 나타나 있다. 제안한 퍼지 제어기의 구현 과정은 다음과 같다. 각 모듈은 VHDL 언어에 의해서 기술된 뒤, Synopsys사의 FPGA 컴파일러에 의해 합성된다. 합성된 각 모듈은 Xilinx사의 XactStep 6.0에 의해 최적화 및 배치, 배선이 이루어진다. 얻어진 Xilinx rawbit 파일은 VCC사의 r2h에 의해 C 언어의 header 파일 형태의 하드웨어 object로 변환된다. C언어 형태의 하드웨어 object를 포함하는 응용 제어 프로그램이 C 컴파일러에 의해 컴파일된 후, 이 실행 파일이 재구성 가능한 FPGA 시스템 상에 다운로드된다. 제안한 퍼지 제어기를 EVCI 보드 상에 동적으로 구현하여 트럭 후진 주차 제어에 사용할 때 걸리는 시간을 Synopsys사의 VHDL 시뮬레이터와 워크스테이션상에서 C언어에 의해 구현하여 트럭 후진 주차 제어에 사용할 때 걸리는 시간을 각각 비교하였다.