• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.4A
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• pp.415-422
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• 2004

DSRC provides high speed radio link between Road Side Equipment and On-Board Equipment within the narrow communication area. In this paper, a 5.8 GHz down-conversion mixer for DSRC communication system was designed and fabricated using 0.8 ${\mu}{\textrm}{m}$ SiGe HBT process technology and RF/LO matching circuits, RF/LO input balun circuits, and If output balun circuit were all integrated on chip. The chip size of fabricated mixer was 1.9 mm${\times}$1.3 mm and the measured performance was 7.5 ㏈ conversion gain, －2.5 ㏈m input IP3, 46 ㏈ LO to RF isolation, 56 ㏈ LO to IF isolation, current consumption of 21 mA for 3.0 V supply voltage.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4A
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• pp.350-357
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• 2005

DSRC provides high speed radio link between Road Side Equipment and On-Board Equipment within the narrow communication area. In this paper, a 5.8 GHz up-conversion mixer for DSRC communication system was designed and fabricated using 0.8 m SiGe HBT process technology and IF/LO/RF matching circuits, IF/LO input balun circuits, and RP output balun circuit were all integrated on chip. The chip size of fabricated mixer was $2.7mm\times1.6mm$ and the measured performance was 3.5 dB conversion gain, -12.5 dBm output IP3, 42 dB LO to If isolation, 38 dB LO to RF isolation, current consumption of 29 mA for 3.0 V supply voltage.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.1A
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• pp.104-112
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• 2005

Some design techniques for high speed and low power pipelined 8-bit ADC are described. To perform high-speed operation with relatively low power consumption, open loop architecture is adopted, while closed loop architecture (with MDAC) is used in conventional pipeline ADC. A distributed track and hold amplifier and a cascading structure are also adopted to increase the sampling rate. To reduce the power consumption and the die area, the number of amplifiers in each stage are optimized and reduced with proposed zero-crossing point generation method. At 500-MHz sampling rate, simulation results show that the power consumption is 210mW including digital logic with 1.8V power supply. And the targeted ADC achieves ENOB of about 8-bit with input frequency up to 200-MHz and input range of 1.2Vpp (Differential). The ADC is designed using a $0.18{\mu}m$ 6-Metal 1-Poly CMOS process and occupies an area of $900{\mu}m{\times}500{\mu}m$

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.4
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• pp.303-309
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• 2013

A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described. An input voltage level detector circuit has been designed to overcome the disadvantages of the flash ADC which consume most of the dynamic power dissipation due to comparators array. In this work, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector. The specific clock signal generated by the detector is applied to turn the corresponding latched comparators on and the rest of the comparators off. This ADC consumes 68.82mW with a single power supply of 1.2V and achieves 4.9 effective number of bits for input frequency up to 1MHz at 500 MS/s. Therefore it results in 4.75pJ/step of Figure of Merit (FoM). The chip is fabricated in 0.13-um CMOS process.

• Journal of Advanced Navigation Technology
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• v.27 no.2
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• pp.203-208
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• 2023

In this study, we propose a method to improve the precision of contact resistance measurement circuits using constant current method and voltage drop method, and implement a dashboard that monitors the measured data of contact resistance measurement systems through MQTT broker server. The contact resistance measurement system measures the resistance value and transmits the measured value to the MQTT broker server using wireless communications. This developed dashboard uses Node-RED and Node-RED-Dashboard to receive the resistance values of up to four contact resistance measurement systems and show them to user's monitor screen. Users can manage multiple measurement data using a single dashboard and easily interface with other devices through the MQTT broker server. Through the experimental results from real data measurements, the relative standard deviation about precision is improved to average 40.37% and maximum 64.73% respectively.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.12
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• pp.7292-7301
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• 2014

With the development of IT Info-Communications technology, the vehicle with a combination of wireless-communication technology has resulted in significant research into the convergence of the component of existing traffic with information, electronics and communication technology. Intelligent Vehicle Communication is a Machine-to-Machine (M2M) concept of the Vehicle-to-Vehicle. The Vehicle-to-Infrastructure communication consists of safety and the ease of transportation. Security technologies must precede the effective Intelligent Vehicle Communication Structure, unlike the existing internet environment, where high-speed vehicle communication is with the security threats of a wireless communication environment and can receive unusual vehicle messages. In this paper, the Vehicle Identification number between the V2I and the secure message communication protocol was proposed using hash functions and a time stamp, and the validity of the vehicle was assessed. The proposed system was the performance evaluation section compared to the conventional technique at a rate VPKI aspect showed an approximate 44% reduction. The safety, including authentication, confidentiality, and privacy threats, were analyzed.

• Journal of Broadcast Engineering
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• v.17 no.5
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• pp.756-764
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• 2012

In current HEVC, prediction pixels are finally calculated by linear-function interpolation on two reference pixels. It is hard to expect good performance on the case of occurring large difference between two reference pixels. This paper decides more accurate prediction pixel values than current HEVC using linear function. While existing prediction process only uses two reference pixels, proposed method uses DCT-IF. DCT-IF analyses frequency characteristics of more than two reference pixels in frequency domain. And proposed method calculates prediction value adaptively by using linear-function, DCT-IF and cubic-function to decide more accurate interpolation value than to only use linear function. Cubic-function has a steep slope than linear-function. So, using cubic-function is utilized on edge in prediction unit. The complexity of encoder and decoder in HM6.0 has increased 3% and 1%, respectively. BD-rate has decreased 0.4% in luma signal Y, 0.3% in chroma signal U and 0.3% in chroma signal V in average. Through this experiment, proposed adaptive intra prediction method using DCT-IF and cubic-function shows increased performance than HM6.0.

• Journal of IKEEE
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• v.3 no.1 s.4
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• pp.39-49
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• 1999

This paper describes a 1 GHz, low-phase-noise CMOS fractional-N frequency synthesizer with an integrated LC VCO. The proposed frequency synthesizer, which uses a high-order delta-sigma modulator to suppress the fractional spurious tones at all multiples of the fractional frequency resolution offset, has 64 programmable frequency channels with frequency resolution of $f_ref/64$. The measured phase noise is as low as -110 dBc/Hz at a 200 KHz offset frequency from a carrier frequency of 980 MHz. The reference sideband spurs are -73.5 dBc. The prototype is implemented in a $0.5{\mu}m$ CMOS process with triple metal layers. The active chip area is about $4mm^2$ and the prototype consumes 43 mW, including the VCO buffer power consumption, from a 3.3 V supply voltage.

• Communications of the Korean Mathematical Society
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• v.32 no.2
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• pp.305-319
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• 2017

Recently many authors have investigated so-called Aleph (${\aleph}$)-function and its various properties. Here, in this paper, we aim at establishing certain integral formulas involving the Aleph (${\aleph}$)-function. Precisely, integrals with product of Aleph (${\aleph}$)-function with Jacobi polynomials, Bessel Maitland function, general class of polynomials were under consideration. Some interesting special cases of our main result are also considered and shown to be connected with certain known ones.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.11B
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• pp.1939-1947
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• 2000

본 논문에서는 명령어의 효율적인 페치를 위해 분기 타겟 주소 전체를 사용하지 않고 캐쉬 메모리(cache memory) 내의 적은 비트 수로 인덱싱 하여 한 클럭 사이클 안에 최대 4개의 명령어를 다음 파이프라인으로 보내줄 수 있는 방법을 제시한다. 본 프리페치 유닛은 크게 나누어 3개의 영역으로 나눌 수 있는데, 분기에 관련하여 미리 부분적으로 명령어를 디코드 하는 프리디코드(predecode) 블록, 타겟 주소(NTA : Next Target Address) 테이블 영역을 추가시킨 명령어 캐쉬(instruction cache) 블록, 전체 유닛을 제어하고 가상 주소를 관리하는 프리페치(prefetch) 블록으로 나누어진다. 사용된 명령어들은 SPARC(Scalable Processor ARChitecture) V9에 기준 하였고 구현은 Verilog-HDL(Hardwave Description Language)을 사용하여 기능 수준으로 기술되고 검증되었다. 구현된 프리페치 유닛은 명령어 흐름에 분기가 존재하더라도 단일 사이클 안에 4개까지의 명령어들을 정확한 예측 하에 다음 파이프라인으로 보내줄 수 있다. 또한 NTA를 사용한 방법은 같은 수의 레지스터 비트를 사용하였을 때 BTB(Branch Target Buffer)를 사용하는 방법과 비교하여 2배정도 많은 개수의 분기 명령 주소를 저장할 수 있는 장점이 있다.