• 제목/요약/키워드: Up-Scaling

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Scaling Up Study of Exopolysaccharide Production through Mycelial Submerged Cultivation of Ganoderma lucidum (영지의 액체배양에 의한 세포외 다당 생산의 Scale Up 연구)

  • Lee, Hak-Su;Lee, Shin-Young
    • KSBB Journal
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    • v.24 no.3
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    • pp.303-311
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    • 2009
  • A scaling up study for the exopolysaccharide (EPS) production by submerged culture of Ganoderma lucidum was carried out in jar fermenter systems (2.6, 20 and 75 L) under bi-staged pH process. Profiles of dissolved oxygen (DO) and volumetric coefficient of oxygen transfer ($k_La$) as a function of operating variables (agitation speed and aeration rate) was investigated, and a correlation between $k_La$ and operating variables was analysed statistically. Under bi-staged pH process, no limitation of DO was observed at agitation speeds tested in the range of 200 and 600 rpm, and the highest EPS production was obtained at the level of DO of $40{\sim}80%$. From the regression analysis, the relation between $k_La$, gas velocity (Vs), stirrer speed (N) and impeller diameter (Di) could be expressed as : $$k_La=0.555{\times}Vs^{0.42}{\times}(N^3{\times}Di^2)^{0.33}\;(R^2=0.925,\;p<0.05)$$ It was found that under 2.6 L jar fermenter, the optimum agitation speed and aeration rate was 400 rpm and 1 vvm, respectively, obtaining the EPS production of 15.43 g/L. Under the submerged cultivation of G. lucidum in jar fermenters of $2.6{\sim}75\;L$, the similar EPS yields at each fermenter were achieved during scaling up based on $k_La$, and $k_La$ value for maximum EPS production was $85.4{\pm}26.70\;h^{-1}$.

An Efficient Multidimensional Scaling Method based on CUDA and Divide-and-Conquer (CUDA 및 분할-정복 기반의 효율적인 다차원 척도법)

  • Park, Sung-In;Hwang, Kyu-Baek
    • Journal of KIISE:Computing Practices and Letters
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    • v.16 no.4
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    • pp.427-431
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    • 2010
  • Multidimensional scaling (MDS) is a widely used method for dimensionality reduction, of which purpose is to represent high-dimensional data in a low-dimensional space while preserving distances among objects as much as possible. MDS has mainly been applied to data visualization and feature selection. Among various MDS methods, the classical MDS is not readily applicable to data which has large numbers of objects, on normal desktop computers due to its computational complexity. More precisely, it needs to solve eigenpair problems on dissimilarity matrices based on Euclidean distance. Thus, running time and required memory of the classical MDS highly increase as n (the number of objects) grows up, restricting its use in large-scale domains. In this paper, we propose an efficient approximation algorithm for the classical MDS based on divide-and-conquer and CUDA. Through a set of experiments, we show that our approach is highly efficient and effective for analysis and visualization of data consisting of several thousands of objects.

A Fast-Locking Fractional-N PLL with Multiple Charge Pumps and Capacitance Scaling Scheme (Capacitance Scaling 구조와 여러 개의 전하 펌프를 이용한 고속의 ${\Sigma}{\Delta}$ Fractional-N PLL)

  • Kwon, Tae-Ha
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.10 s.352
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    • pp.90-96
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    • 2006
  • A novel ${\Sigma}{\Delta}$ fractional-N PLL architecture for fast locking and fractional spur suppressing is proposed based on the capacitance scaling scheme. It changes the effective capacitance of loop filter (LF) by increasing and decreasing current to the capacitor via different paths with multiple charge pumps. The effective capacitance of loop filter (LF) can be scaled up/down depending on operating status while keeping LF capacitors small enough to be integrated into a single PLL chip. Fractional spurs suppressing have been achieved by reducing the magnitude of charge pump current when the PLL is in-lock without degrading fast locking characteristic. It has been simulated by HSPICE in a CMOS $0.35{\mu}m$ process, and shows flat locking time is less than $8{\mu}s$ with the small size of LF capacitors, 200pF and 17pF, and $2.8k{\Omega}$ resistor.

Evaluation of Hybrid Downscaling Method Combined Regional Climate Model with Step-Wise Scaling Method (RCM과 단계적 스케일링기법을 연계한 혼합 상세화기법의 적용성 평가)

  • Lee, Moon Hwan;Bae, Deg Hyo
    • Journal of Korea Water Resources Association
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    • v.46 no.6
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    • pp.585-596
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    • 2013
  • The objective of this study is to evaluate the hybrid downscaling method combined Step-Wise Scaling (SWS) method with Regional Climate Model (RCM) simulation data for climate change impact study on hydrology area. The SWS method is divided by 3 categories (extreme event, dry event and the others). The extreme events, wet-dry days and the others are corrected by using regression method, quantile mapping method, mean & variance scaling method. The application and evaluation of SWS method with 3 existing and popular statistical techniques (linear scaling method, quantile mapping method and weather generator method) were performed at the 61 weather stations. At the results, the accuracy of corrected simulation data by using SWS are higher than existing 3 statistical techniques. It is expected that the usability of SWS method will grow up on climate change study when the use of RCM simulation data are increasing.

Single Image Super-Resolution Using CARDB Based on Iterative Up-Down Sampling Architecture (CARDB를 이용한 반복적인 업-다운 샘플링 네트워크 기반의 단일 영상 초해상도 복원)

  • Kim, Ingu;Yu, Songhyun;Jeong, Jechang
    • Journal of Broadcast Engineering
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    • v.25 no.2
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    • pp.242-251
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    • 2020
  • Recently, many deep convolutional neural networks for image super-resolution have been studied. Existing deep learning-based super-resolution algorithms are architecture that up-samples the resolution at the end of the network. The post-upsampling architecture has an inefficient structure at large scaling factor result of predicting a lot of information for mapping from low-resolution to high-resolution at once. In this paper, we propose a single image super-resolution using Channel Attention Residual Dense Block based on an iterative up-down sampling architecture. The proposed algorithm efficiently predicts the mapping relationship between low-resolution and high-resolution, and shows up to 0.14dB performance improvement and enhanced subjective image quality compared to the existing algorithm at large scaling factor result.

Algorithm for Scaling of the Decoder inputs with Variable Transmission Rate (가변 전송율을 갖는 디코더 입력의 스케일링을 위한 알고리듬)

  • 진익수;심재영
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.7 no.5
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    • pp.887-892
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    • 2003
  • In this paper, we propose a simple scaling algorithm for CDMA mobile communications where a voice traffic signals are transmitted by individual one of several data rates at every frames. The traditional method is based on using look-up table called SMT(symbol metric table), but the proposed algorithm is real-time direct scaling method through simple bit manipulations without lookup table. The bit error rate performance is calculated by computer simulation over AWGN and Rayleigh fading channels. From the results, it is shown that the proposed algorithm outperforms the traditional SMT method on Rayleigh channel by 0.3∼0.8dB, while achieving the less H/W complexity.

A Dynamic Voltage Scaling Algorithm for Low-Energy Hard Real-Time Applications using Execution Time Profile (실행 시간 프로파일을 이용한 저전력 경성 실시간 프로그램용 동적 전압 조절 알고리즘)

  • 신동군;김지홍
    • Journal of KIISE:Computer Systems and Theory
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    • v.29 no.11
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    • pp.601-610
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    • 2002
  • Intra-task voltage scheduling (IntraVS), which adjusts the supply voltage within an individual task boundary, is an effective technique for developing low-power applications. In this paper, we propose a novel intra-task voltage scheduling algorithm for hard real-time applications based on average-case execution time. Unlike the conventional IntraVS algorithm where voltage scaling decisions are based on the worst-case execution cycles, tile proposed algorithm improves the energy efficiency by controlling the execution speed based on average-case execution cycles while meeting the real-time constraints. The experimental results using an MPEG-4 decoder program show that the proposed algorithm reduces the energy consumption by up to 34% over conventional IntraVS algorithm.

Multi-Valued Logic Device Technology; Overview, Status, and Its Future for Peta-Scale Information Density

  • Kim, Kyung Rok;Jeong, Jae Won;Choi, Young-Eun;Kim, Woo-Seok;Chang, Jiwon
    • Journal of Semiconductor Engineering
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    • v.1 no.1
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    • pp.57-63
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    • 2020
  • Complementary metal-oxide-semiconductor (CMOS) technology is now facing a power scaling limit to increase integration density. Since 1970s, multi-valued logic (MVL) has been considered as promising alternative to resolve power scaling challenge for increasing information density up to peta-scale level by reducing the system complexity. Over the past several decades, however, a power-scalable and mass-producible MVL technology has been absent so that MVL circuit and system implementation have been delayed. Recently, compact MVL device researches incorporating multiple-switching characteristics in a single device such as 2D heterojunction-based negative-differential resistance (NDR)/transconductance (NDT) devices and quantum-dot/superlattices-based constant intermediate current have been actively performed. Meanwhile, wafer-scale, energy-efficient and variation-tolerant ternary-CMOS (T-CMOS) technology has been demonstrated through commercial foundry. In this review paper, an overview for MVL development history including recent studies will be presented. Then, the status and its future research direction of MVL technology will be discussed focusing on the T-CMOS technology for peta-scale information processing in semiconductor chip.

Effect of design spectral shape on inelastic response of RC frames subjected to spectrum matched ground motions

  • Ucar, Taner;Merter, Onur
    • Structural Engineering and Mechanics
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    • v.69 no.3
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    • pp.293-306
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    • 2019
  • In current seismic design codes, various elastic design acceleration spectra are defined considering different seismological and soil characteristics and are widely used tool for calculation of seismic loads acting on structures. Response spectrum analyses directly use the elastic design acceleration spectra whereas time history analyses use acceleration records of earthquakes whose acceleration spectra fit the design spectra of seismic codes. Due to the fact that obtaining coherent structural response quantities with the seismic design code considerations is a desired circumstance in dynamic analyses, the response spectra of earthquake records used in time history analyses had better fit to the design acceleration spectra of seismic codes. This paper evaluates structural response distributions of multi-story reinforced concrete frames obtained from nonlinear time history analyses which are performed by using the scaled earthquake records compatible with various elastic design spectra. Time domain scaling procedure is used while processing the response spectrum of real accelerograms to fit the design acceleration spectra. The elastic acceleration design spectra of Turkish Seismic Design Code 2007, Uniform Building Code 1997 and Eurocode 8 are considered as target spectra in the scaling procedure. Soil classes in different seismic codes are appropriately matched up with each other according to $V_{S30}$ values. The maximum roof displacements and the total base shears of considered frame structures are determined from nonlinear time history analyses using the scaled earthquake records and the results are presented by graphs and tables. Coherent structural response quantities reflecting the influence of elastic design spectra of various seismic codes are obtained.