• Title/Summary/Keyword: Up-Converter

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OXIDATION CHARACTERISTICS OF PARTICULATE MATTER ON DIESEL WARM-UP CATALYTIC CONVERTER

  • Choi, B.C.;Yoon, Y.B.;Kang, H.Y.;Lim, M.T.
    • International Journal of Automotive Technology
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    • v.7 no.5
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    • pp.527-534
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    • 2006
  • Modern passenger cars with diesel engines are equipped with DOC(diesel oxidation catalyst) for the purpose of reducing HC and CO in the exhaust stream. Cold start exhaust emissions pose troubles here as on gasoline engine vehicles. As a result, some of the diesel passenger cars roll off todays the assembly lines with WCC(warm-up catalytic converter). Oxidation characteristics of the particulates in WCC is analyzed in this study by EEPS(engine exhaust particulate size spectrometer). The maximum number of PM is found to come out of WCC in sizes near 10nm when an HSDI diesel engine is operated under the conditions of high speed and medium to heavy load. When the temperature of the WCC exceeds $300^{\circ}C$, the number of PM smaller than 30 nm in diameter sharply increases upon passing through the WCC. Total mass of emitted PM gets reduced downstream of the WCC under low speed and light load conditions due to adsorption of PM onto the catalyst. Under conditions of high speed and medium to heavy load, the relatively large PM shrink or break into fine particles during oxidation process within the WCC, which results in more mass fraction of fine particles downstream of the WCC.

Implementation of Self-frequency Synchronizing Circuit using Single-sideband Up-converter and Image Rejection Mixer (단측파대 상향변환기와 이미지제거 혼합기를 이용한 자기동조회로의 구현)

  • Yeom, Seong-Hyeon;Kim, Tae-Young;Kim, Tae-Hyun;Park, Boem-June
    • Journal of the Korea Institute of Military Science and Technology
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    • v.13 no.6
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    • pp.1058-1063
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    • 2010
  • In this paper, we designed self-frequency synchronizing circuit using image rejection mixer(IRM) and single-sideband(SSB) up-converter which can effectively eliminate the image frequencies occurred in multi-channel super-heterodyne receivers and help us to match inter-channel phase. Also the self-frequency synchronizing circuit simplifies system because there need no extra devices for making intermediate frequency(IF) by creating the local signal within several nanoseconds by means of generating the same frequency of IF signal and modulating radio frequency(RF) signal. We adopt the limiting amplifier for the purpose of protecting the circuit from spurious signals which come from the front end side having wide instantaneous bandwidth characteristics and constantly injecting same level into the input local signal of IRM. The IRM we fabricated has image rejection ratio of 27dB, which is good over 7dB for foreign company's. Also, the SSB up-converter we fabricated has 1dB compression point of 18dBm, which is good over 16dB for foreign company's. And the size is compact about one-forth.

Interleaved High Step-Up Boost Converter

  • Ma, Penghui;Liang, Wenjuan;Chen, Hao;Zhang, Yubo;Hu, Xuefeng
    • Journal of Power Electronics
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    • v.19 no.3
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    • pp.665-675
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    • 2019
  • Renewable energy based on photovoltaic systems is beginning to play an important role to supply power to remote areas all over the world. Owing to the lower output voltage of photovoltaic arrays, high gain DC-DC converters with a high efficiency are required in practice. This paper presents a novel interleaved DC-DC boost converter with a high voltage gain, where the input terminal is interlaced in parallel and the output terminal is staggered in series (IPOSB). The IPOSB configuration can reduce input current ripples because two inductors are interlaced in parallel. The double output capacitors are charged in staggered parallel and discharged in series for the load. Therefore, IPOSB can attain a high step-up conversion and a lower output voltage ripple. In addtion, the output voltage can be automatically divided by two capacitors, without the need for extra sharing control methods. At the same time, the voltage stress of the power devices is lowered. The inrush current problem of capacitors is restrained by the inductor when compared with high gain converters with a switching-capacitor structure. The working principle and steady-state characteristics of the converter are analyzed in detail. The correctness of the theoretical analysis is verified by experimental results.

A 1.8 V 0.18-μm 1 GHz CMOS Fast-Lock Phase-Locked Loop using a Frequency-to-Digital Converter

  • Lee, Kwang-Hun;Jang, Young-Chan
    • Journal of information and communication convergence engineering
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    • v.10 no.2
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    • pp.187-193
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    • 2012
  • A 1 GHz CMOS fast-lock phase-locked loop (PLL) is proposed to support the quick wake-up time of mobile consumer electronic devices. The proposed fast-lock PLL consists of a conventional charge-pump PLL, a frequency-to-digital converter (FDC) to measure the frequency of the input reference clock, and a digital-to-analog converter (DAC) to generate the initial control voltage of a voltage-controlled oscillator (VCO). The initial control voltage of the VCO is driven toward a reference voltage that is determined by the frequency of the input reference clock in the initial mode. For the speedy measurement of the frequency of the reference clock, an FDC with a parallel architecture is proposed, and its architecture is similar to that of a flash analog-to-digital converter. In addition, the frequency-to-voltage converter used in the FDC is designed simply by utilizing current integrators. The circuits for the proposed fast-lock scheme are disabled in the normal operation mode except in the initial mode to reduce the power consumption. The proposed PLL was fabricated by using a 0.18-${\mu}m$ 1-poly 6-metal complementary metal-oxide semiconductor (CMOS) process with a 1.8 V supply. This PLL multiplies the frequency of the reference clock by 10 and generates the four-phase clock. The simulation results show a reduction of up to 40% in the worstcase PLL lock time over the device operating conditions. The root-mean-square (rms) jitter of the proposed PLL was measured as 2.94 ps at 1 GHz. The area and power consumption of the implemented PLL are $400{\times}450{\mu}m^2$ and 6 mW, respectively.

DCM DC-DC Converter for Mobile Devices (모바일 기기용 DCM DC-DC Converter)

  • Jung, Jiteck;Yun, Beomsu;Choi, Joongho
    • Journal of IKEEE
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    • v.24 no.1
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    • pp.319-325
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    • 2020
  • In this paper, a discontinuous-conduction mode (DCM) DC-DC buck converter is presented for mobile device applications. The buck converter consists of compensator for stable operations, pulse-width modulation (PWM) logic, and power switches. In order to achieve small hardware form-factor, the number of off-chip components should be kept to be minimum, which can be realized with simple and efficient frequency compensation and digital soft start-up circuits. Burst-mode operation is included for preventing the efficiency from degrading under very light load condition. The DCM DC-DC buck converter is fabricated with 0.18-um BCDMOS process. Programmable output with external resistors is typically set to be 1.8V for the input voltage between 2.8 and 5.0V. With a switching frequency of 1MHz, measured maximum efficiency is 92.6% for a load current of 100mA.

25 kW, 300 kHz High Step-Up Soft-Switching Converter for Next-Generation Fuel Cell Vehicles (차세대 연료전지 자동차용 25kW, 300kHz 고승압 소프트 스위칭 컨버터)

  • Kim, Sunju;Tran, Hai Ngoc;Kim, Jinyoung;Kieu, Huu-Phuc;Choi, Sewan;Park, Jun-Sung;Yoon, Hye-Sung
    • The Transactions of the Korean Institute of Power Electronics
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    • v.26 no.6
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    • pp.404-410
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    • 2021
  • This paper proposes a high step-up converter with zero-voltage transition (ZVT) cell for fuel cell electric vehicle. The proposed converter applies a ZVT cell to a dual floating output boost converter (DFOBC) so that not only the main switch but also the ZVT switch can achieve full-range soft switching. The current rating of the ZVT switch is 17% of the main switch. The proposed converter has high reliability in that no timing issue occurs. Therefore, online calculation is not required. The minimum turn-on time of the ZVT switch that guarantees soft switching at all loads and input/output voltage is obtained by analysis. In addition, the proposed DFOBC allows the use of a 650 V device even at 800 V output and has the advantage of being able to boost the voltage by 3.5 times with 0.56 duty. Planar coupled inductor with PCB winding was successfully implemented with the converter operated at 300 kHz. The 25 kW prototype achieves peak efficiency of 99% and power density of 63 kW/L.

Soft-Switching Boost Chopper Type DC-DC Power Converter with a Single Auxiliary Passive Resonant Snubber

  • Nakamura Mantaro;Myoui Takeshi;Abudullh Al Mamun;Nakaoka Mutsuo
    • Proceedings of the KIPE Conference
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    • 2001.10a
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    • pp.256-260
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    • 2001
  • This paper presents boost and buck and buck-boost DC-DC converter circuit topologies of high-frequency soft switching transition PWM chopper type DC-DC high power converters with a single auxiliary passive resonant snubber. In the proposed boost power converter circuits operating under a principle of ZCS turn-on and ZVS turn-off commutation schemes, the capacitor and inductor in the auxiliary passive resonant circuit works as the loss less resonant snubber. In addition to this, the switching voltage and current peak stresses as well as EMI and RFI noises can be basically reduced by this single passive resonant snubber. Moreover, it is proved that converter circuit topologies with a passive resonant snubber are capable of solving some problems of the conventional hard switching PWM processing based on high-ferquency pulse modulation operation principle. The simulation results of this converter are discussed as compared with the experimental ones. The effectiveness of this power converter with a single passive resonant snubber is verified by the 5kW experimental breadboad set up.

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Highly Efficient AC-DC Converter for Small Wind Power Generators

  • Ryu, Hyung-Min
    • Journal of Power Electronics
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    • v.11 no.2
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    • pp.188-193
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    • 2011
  • A highly efficient AC-DC converter for small wind power generation systems using a brushless DC generator (BLDCG) is presented in this paper. The market standard AC-DC converter for a BLDCG consists of a three-phase diode rectifier and a boost DC-DC converter, which has an IGBT and a fast recovery diode (FRD). This kind of two-stage solution basically suffers from a large amount of conduction loss and the efficiency greatly decreases under a light load, or at a low current, because of the switching devices with a P-N junction. In order to overcome this low efficiency, especially at a low current, a three-phase bridgcless converter consisting of three upper side FRDs and three lower side Super Junction FETs is presented. In the overall operating speed region, including the cut-in speed, the efficiency of the proposed converter is improved by up to 99%. Such a remarkable result is validated and compared with conventional solutions by calculating the power loss based on I-V curves and the switching loss data of the adopted commercial switches and the current waveforms obtained through PSIM simulations.

The Controller Design of Bi-directional DC-DC Converter for a Fuel Cell Energy Storage System (연료전지용 커패시터 충.방전을 위한 양방향 DC-DC 컨버터 제어기 설계)

  • Kim, Seung-Min;Yang, Seung-Dae;Choi, Ju-Yeop;An, Jin-Woong;Lee, Sang-Chul;Lee, Dong-Ha
    • 한국태양에너지학회:학술대회논문집
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    • 2012.03a
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    • pp.222-228
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    • 2012
  • This paper presents a design and simulation of bi-directional DC/DC boost converter for a fuel cell system. In this paper, we analyze the equivalent model of both a boost converter and a buck converter. Also we propose the controller of bi-directional DC-DC converter, which has buck mode of charging a capacitor and boost mode of discharging a capacitor. In order to design a controller, we draw bode plots of the control-to-output transfer function using specific parameters and incorporate 3pole-2zero compensator in a closed loop. As a result, it has increased PM(Phase Margin) for better dynamic performance. The proposed bi-directional DC-DC converter's 3pole-2zero compensation method has been verified with computer simulation and simulation results obtained demonstrates the validity of the proposed control scheme.

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SiC Based Single Chip Programmable AC to DC Power Converter

  • Pratap, Rajendra;Agarwal, Vineeta;Ravindra, Kumar Singh
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.6
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    • pp.697-705
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    • 2014
  • A single chip Programmable AC to DC Power Converter, consisting of wide band gap SiC MOSFET and SiC diodes, has been proposed which converts high frequency ac voltage to a conditioned dc output voltage at user defined given power level. The converter has high conversion efficiency because of negligible reverse recovery current in SiC diode and SiC MOSFET. High frequency operation reduces the need of bigger size inductor. Lead inductors are enough to maintain current continuity. A complete electrical analysis, die area estimation and thermal analysis of the converter has been presented. It has been found that settling time and peak overshoot voltage across the device has reduced significantly when SiC devices are used with respect to Si devices. Reduction in peak overshoot also increases the converter efficiency. The total package substrate dimension of the converter circuit is only $5mm{\times}5mm$. Thermal analysis performed in the paper shows that these devices would be very useful for use as miniaturized power converters for load currents of up to 5-7 amp, keeping the package thermal conductivity limitation in mind. The converter is ideal for voltage requirements for sub-5 V level power supplies for high temperatures and space electronics systems.