• 전기전자학회논문지
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• 제23권1호
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• pp.273-279
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• 2019

A high boost dc-dc converter based on the switched-inductor cell (SL-cell) is suggested in this paper. The suggested converter can provide a high voltage gain that is more than 6. Moreover, the voltage gain can be easily increased by extending a SL cell or a modular voltage boost stage. This paper shows the key waveforms, the operating principles at the continuous conduction mode (CCM), and a comparison between the suggested converter and the other non-isolated converters. In addition, the extension of the suggested converter is presented. The simulation results were shown to reconfirm the theoretical analysis.

• 전력전자학회논문지
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• 제25권6호
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• pp.484-489
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• 2020

This study proposes a new soft-switching three-level flying capacitor converter with low filter inductance. The proposed converter can achieve zero voltage switching (ZVS) turn-on of all switches by using auxiliary components La and Ca. It can also reduce filter inductance because the applied voltage of the filter inductor is decreased by using the flying capacitor. Furthermore, filter inductance can be reduced because the operating frequency of the filter inductor is doubled by the phase shifting between switches S3 and S4. The operation principle, design of passive components for ZVS turn-on, interleaving effects, and comparison of different topologies are presented. The experimental waveforms of a 1 kW two-phase interleaved converter prototype are provided to verify the validity of the proposed converter.

• 전력전자학회논문지
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• 제17권6호
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• pp.507-515
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• 2012

DC-DC converter which composed of LLC resonant converter, operated by fixed switching frequency with fixed duty cycle (50%), and flyback converter to provide constant output voltage($400V_{DC}$) with variation of input voltage($30-60V_{DC}$) is proposed in this paper. To obtain constant output voltage($400V_{DC}$), flyback converter is not operated in case of above the maximum input voltage($60V_{DC}$) and operated as the input voltage decreases to below 60VDC. Therefore, flyback converter can be designed to the 50% power rating of the maximum power in the proposed DC-DC converter. Operation modes and voltage gain characteristics were analyzed and a 360W prototype converter was tested to verify the proposed converter.

• 센서학회지
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• 제24권6호
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• pp.359-363
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• 2015

This paper proposes an algorithm that reduces the conversion time of a single-slope A/D converter (SSADC) that has n-bit resolution, which typically is limited by conversion time taking up to $2^n$ clock cycles for an operation. To improve this situation, we have researched a novel hybrid-type A/D converter that consists of a pseudo-pipeline A/D converter and a conventional SSADC. The pseudo-pipeline A/D converter, using a single-stage of analog components, determines the most significant bits (MSBs) or upper bits and the conventional SSADC determines the remaining bits. Therefore, the modified SSADC, similar to the hybrid-type A/D converter, is able to significantly reduce the conversion time because the pseudo-pipeline A/D converter, which determines the MSBs (or upper bits), does not rely on a clock. The proposed A/D converter was designed using a $0.35-{\mu}m$ 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) technology process; additionally, its characteristics were simulated.

• 한국산학기술학회논문지
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• 제17권6호
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• pp.715-720
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• 2016

본 논문에서는, 휴대기기를 위한 PWM(Pulse Width Modulation), 전압모드 DC-DC 승압형 컨버터를 제안한다. 제안하는 컨버터는 현재 소형화 되어가고 있는 휴대기기 시장에 적합하도록 1 MHz의 스위칭 주파수를 사용하여 칩 면적을 줄였다. 제안하는 DC-DC 컨버터는 전력단과 제어단으로 이루어지며 전력단은 인덕터, 출력 커패시터, MOS 트랜지스터 등으로 구성되며 제어단은 연산증폭기, 밴드갭 회로, 소프트 스타트 블록, 히스테리시스 비교기와 비겹침 드라이버로 구성된다. 설계된 회로는 히스테리시스 비교기와 논오버랩 드라이버를 사용하여 낮은 전압에서 구동되는 휴대기기의 잡음의 영향을 줄이고 출력전압 리플을 감소시켰다. 제안하는 회로는 1-poly 6-metal CMOS 매그나칩/하이닉스 $0.18{\mu}m$ 공정을 사용하여 레이아웃을 진행하였다. 설계된 컨버터는 입력 전압 3.3 V, 출력전압 5 V, 출력전류 100 mA 출력전압 대비 1%의 출력 전압 리플과 1 MHz의 스위칭 주파수의 특성을 갖는다. 본 논문에서 제안하는 승압형 DC-DC 컨버터는 PDA, 휴대폰, 노트북 등 휴대용 전자기기 시장에 맞는 고효율, 소형화 컨버터로서 유용하게 사용 될 것으로 사료된다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2006년도 전력전자학술대회 논문집
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• pp.25-27
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• 2006

This paper proposes a new full ZVS-range asymmetrical half bridge converter. It uses the variable transient current build-up technique with the load variations. The current build-up is accomplished by using the secondary synchronous switch control. Due to the blocking capacitor in secondary side, the voltage applied to leakage inductor varies with the load variations during current build-up period. Therefore, the unnecessary current build-up of leakage inductor current in heavy load condition is prevented and more current build-up in medium and light load condition is achieved for ZVS operation. That is, the variant current build-up with the load variation is accomplished for the ZVS operation. Furthermore, the DC offset of the transformer magnetizing current is also eliminated and the utilization of magnetic core is maximized.

• 전력전자학회논문지
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• 제17권4호
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• pp.322-329
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• 2012

This paper proposes a non-isolated bidirectional soft-switching converter with high voltage for high step-up/down and high power applications. Compared to the conventional boost converter the proposed converter can achieve approximately doubled voltage gain using the same duty cycle. The voltage ratings of the switch and diode are reduced to half, which result in the use of devices with lower $R_{DS(ON)}$ and on drop leading to reduced conduction losses. Also, voltage ratings of the passive components are reduced, and therefore the total energy volume is reduced to half. Further, the switch is turned on with ZVS in the CCM operation which results in negligible surge caused leading to reduced switching losses. The validity of the proposed converter is proved through a 10kW prototype.

• Journal of Electrical Engineering and Technology
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• 제13권6호
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• pp.2441-2446
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• 2018

This paper presents a radio frequency-to-direct current (RF-to-DC) converter for special RF power harvesting application at 915 MHz. The major featured components of the proposed RF-to-DC converter is the combination of a cross-coupled rectifier and an active diode: first, the cross-coupled rectifier boosts the input voltage to desired level, and an active diode blocks the reverse current, respectively. A prototype was implemented using $0.18{\mu}m$ CMOS technology, and the performance was proven from the fact that the targeted RF harvesting system's full-operation with higher power efficiency; even if the system's input power gets lower (e.g., from nominal 0 to min. -12 dBm), the proposed RF-to-DC converter constantly provides 1.47 V, which is exactly the voltage level to drive follow up system components like DC-to-DC converter and so on. And, maximum power conversion efficiency is 82 % calculated from the 0 dBm input power, 2.3 mA load current.

• 한국컴퓨터정보학회논문지
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• 제7권4호
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• pp.115-120
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• 2002

본 논문은 Field Programmable Gate Array (FPGA)와 디지털 신호처리 소자를 이용한 IS-95 CDMA신호 처리기 FPGA와 고속의 ADC/DAC를 이용한 기저대역과 중간주파수(IF)의 디지털 변환기 그리고 주파수 상·하향 변환기를 구현하였다. IS-95 CDMA 채널 처리기는 짧은 PN 코드 발생기와 왈쉬 코드 발생기로 파일롯 채널의 신호를 발생시킨다. 디지털 IF는 FPGA, 디지털 송·수신 신호처리 소자와 고속의 ADC/DAC로 구성하였다. 주파수 상·하향 변환기는 필터, 믹서, 디지털 감쇠기와 PLL로 구성되어 중간주파수(IF)와 RF 주파수를 변환하였다. 이 구현된 시스템은 IS-95 CDMA 기지국 장비 등에 장착할 수 있다.

• Journal of Power Electronics
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• 제17권5호
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• pp.1186-1194
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• 2017

This paper proposes an improved low frequency Selective Harmonic Mitigation-PWM (SHM-PWM) technique. The proposed method mitigates the low order harmonics of the output voltage up to the $50^{th}$ harmonic well and satisfies the grid codes EN 50160 and CIGRE-WG 36-05. Using a modified criterion for the switching angles, the range of the modulation index for non-linear SHM equations is improved, without increasing the switching frequency of the CHB converter. Due to the low switching frequency of the CHB converter, mitigating the harmonics of the converter up to the $50^{th}$ order and finding a wider modulation index range, the size and cost of the passive filters can be significantly reduced with the proposed technique. Therefore, the proposed technique is more efficient than the conventional SHM-PWM. To verify the effectiveness of the proposed method, a 7-level Cascaded H-bridge (CHB) converter is utilized for the study. Simulation and experimental results confirm the validity of the above claims.