• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.891-894
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• 2003

본 논문에서는 3-상 클럭을 이용하여 UP/DOWN 변환을 동시에 수행하는 DC/DC 변환기의 설계에 대해 설명한다. 기존의 UP/DOWN DC/DC 변환기의 경우에는 한 스텝당 변화하는 전압의 양이 많아서 출력에 수십 mV의 리플이 존재하게 된다. 이 리플을 줄이기 위해서는 L, C의 값을 크게 해 주어야하는 문제가 있다. 그러나, 설계된 UP/DOWN DC/DC 변환기는 기존의 UP/DOWN DC/DC 변환기의 구조를 가지면서, 3-상 클럭을 이용하여 한 스텝당 변화하는 전압의 양을 작게 하여 작은 L, C의 값을 가지고도 4mV이하의 출력 리플을 갖는 안정된 전압 변환을 하도록 설계하였다. 설계된 변환기는 0.25㎛ standard CMOS 공정을 이용하여 구현하였다. 구현 된 칩의 면적은 1.8 mm × 0.8 mm이다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.1023-1026
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• 2005

본 논문에서는 SDR(Software Defined Radio) 시스템을 위한 Digital IF(Intermediate Frequency) Up/Down 변환기를 설계하고 성능을 평가하였다. 설계한 시스템은 AD 변환부, DA 변환부 및 Up-Down conversion 기능을 수행하는 FPGA로 구성된다. AD 변환부는 Analog Device 사의 AD6645를 사용하였으며, DA 변환부는 Analog Device 사의 AD9775를 사용하였다. Up-Down conversion 기능을 수행하는 FPGA부는 샘플된 IF 입력을 혼합기와 NCO에 의해 기저대역(DC)으로 다운 시키는 역할을 하며, 14bit의 기저대역(DC) 신호를 혼합기와 NCO에 의해 IF 출력으로 올려주는 역할을 한다. 이러한 설계는 기존의 아날로그 헤테로다인 방식에 비하여 높은 유연성 및 우수한 성능 향상을 보여준다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.804-807
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• 2005

Design Up/Down converters which use Digital IF(Intermediate Frequency) techniques from the present paper, against hereupon performance the criticism. The reason which uses Digital IF techniques is configured of passive elements and the positions IF frequency domains are fixed and they do not use in the position one frequency but, the external fringe land of the board which comes to be configured with Digital IF without from the communication frequency domain which is various there to be a flexibility, the use was under possibility. Like this configuration compares in analog Heterodyne mode of existing and it has the performance upgrade which is excellent it shows a high flexibility.

• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.207-210
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• 2002

This paper describes a design of multiple-mode single-output DC/DC converter which can be used in both up and down conversion. Proposed up/down converter does not produce a negative voltage which is generated in conventional buck-boost type converter. Three types of operation mode(up/down/bypass) are controlled by the input voltage sense and command signals of target output voltage. PFM(pulse frequency modulation) control is adopted and modified for fast tracking and for precise output voltage level with an aid of output voltage sense. Designed DC/DC converter has the performance of less than 5 % ripple and higher than 80 % efficiency. Chip area is 3.50 mm ${\times}$ 2.05 mm with standard 0.35 $\mu\textrm{m}$ CMOS technology.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.961-965
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• 2006

Design Up/Down converters which use Digital IF( Intermediate Frequency) techniques from the present paper, against hereupon performance the criticism. The reason which uses Digital IF techniques is configured of passive elements and the position If frequency domains are fixed and they do not use in the position one frequency but, the external fringe land of the board which comes to be configured with Digital IF without from the communication frequency domain which is various there to be a flexibility, the use was under possibility. Like this configuration compares in analog Heterodyne mode of existing and it has the performance upgrade which is excellent it shows a high flexibility.

• Journal of the Korea Society of Computer and Information
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• v.7 no.4
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• pp.115-120
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• 2002

This paper presents the implementation of IS-95 CDMA signal processor, baseband and Intermediate Frequency(IF) digital converter using Field Programmable Gate Array(FPGA) and ADC/DAC and frequency up/down converter IS-95 CDMA channel processor is generated the pilot channel signal with short PN code and Walsh-code generator. The digital If is composed of FPGA. digital transmit/receive signal processor and high speed analog-to-digital converter(ADC) and digital-to-analog converter(DAC). The frequency up/down converter consisted of filter, mixer, digital attenuator and PLL is analog conversion between intermediate frequency(IF) and baseband. This implemented system can be deployed in the IS-95 CDMA base station device etc.

• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2589-2591
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• 2002

송수신기의 방식에는 직접변환 방식과 기저대역 신호와 LO(Local Oscillator)를 혼합하여 interpolation 기법을 사용하여 중간 주파수 단계까지 up conversion을 하고 두 번째 LO와 IF신호를 혼합하여 RF신호로 변환하여 송신하는 헤테로다인 방식이 존재한다. 본 논문에서는 이런 송수신기 방식 중에서 헤테로다인 방식을 적용하여 QPSK에서의 digital up /down converter를 Simulink 환경에서 설계 및 구현하였다. Up converter는 4배의 interpolation 필터와 4단짜리 cascaded integrate-comb(CIC)필터를 사용하여 입력데이터의 샘플 레이트를 클럭 레이트까지 증가시켰으며, numerically controlled oscillator (NCO)와 mixer를 사용하여 신호를 변조하였다. Down converter의 구조는 up converter와 동일하며 단지 up converter의 반대순서로 구성되어있다. 이런 모든 과정을 Simulink를 이용한 시뮬레이션과 스펙트럼 분석기를 사용하여 검증해 보았다.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.366-370
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• 2003

This paper introduces a new design and fabrication technology of 28 GHz low-cost up and down converter modules for digital microwave radios, The design of the converter module is based on unit circuit blocks, which are to be characterized using a special test fixture. Based on the cascade analysis of the module the 28 GHz up and down converter modules have been designed and implemented. The measured module performance agrees with the cascade analysis. New components such as a tapped edge-coupled filter and a new Ka-band waveguide-to-microstrip transition, which are less sensitive to fabrication tolerances, have been used in the module implementation.

• Journal of IKEEE
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• v.13 no.4
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• pp.82-88
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• 2009

This paper is analyzed for a step up-down DC/DC chopper of high efficiency added electric isolation. The converters of high efficiency are generally made that the power loss of the used semiconductor switching devices is minimized. To achieve high efficiency system, the proposed chopper is constructed by using a partial resonant circuit. The control switches using in the chopper are operated with soft switching by partial resonant method. The control switches are operated without increasing their voltage and current stresses by the soft switching technology. The result is that the switching loss is very low and the efficiency of the chopper is high. The proposed chopper is also added electric isolation which is used a pulse transformer. When the power conversion system is required electric isolation, the proposed chopper is adopted with the converter system development of high efficiency. The soft switching operation and the system efficiency of the proposed chopper are verified by digital simulation and experimental results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.4C
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• pp.380-387
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• 2002

In this paper, the effect of the phase noise of a local oscillator on the ACPR of a transmitter and the reception sensitivity of a receiver to meet the TIA/EIA/IS-98-D for the CDMA mobile station was analyzed. And the optimum condition for performance of the local oscillator was suggested. It was found that the phase noise level of the local oscillator in a receiver and a transmitter should be below -138.3dBc/Hz and -120dBc/Hz, respectively, at 900kHz offset. It was confirmed that the reception sensitivity and ACPR efficiency were satisfactory when the signal of the local oscillator to the down-converter of a receiver with the phase noise level of less than -138.3dBc/Hz is supplied to the up-converter of the transmitter.