• Title/Summary/Keyword: Ultra shallow junctions

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Improvement of Thermal Stability of Ni-Silicide Using Vacuum Annealing on Boron Cluster Implanted Ultra Shallow Source/Drain for Nano-Scale CMOSFETs

  • Shin, Hong-Sik;Oh, Se-Kyung;Kang, Min-Ho;Lee, Ga-Won;Lee, Hi-Deok
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.10 no.4
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    • pp.260-264
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    • 2010
  • In this paper, Ni silicide is formed on boron cluster ($B_{18}H_{22}$) implanted source/drains for shallow junctions of nano-scale CMOSFETs and its thermal stability is improved, using vacuum annealing. Although Ni silicide on $B_{18}H_{22}$ implanted Si substrate exhibited greater sheet resistance than on the $BF_2$ implanted one, its thermal stability was greatly improved using vacuum annealing. Moreover, the boron depth profile, using vacuum post-silicidation annealing, showed a shallower junction than that using $N_2$ annealing.

The effect of annealing conditions on ultra shallow $ p^+-n$ junctions formed by low energy ion implantation (저에너지 이온 주입 방법으로 형성된 박막$ p^+-n$ 접합의 열처리 조건에 따른 특성)

  • 김재영;이충근;홍신남
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.5
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    • pp.37-42
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    • 2004
  • Shallow $p^{+}$-n junctions were formed by preamorphization, low-energy ion implantation and dual-step annealing processes. Germanium ions were implanted into silicon substrates for preamorphization. The dopant implantation was performed into the preamorphized and non-preamorphized substrates using B $F_2$2 ions. Rapid thermal anneal (RTA) and furnace anneal (FA) were employed for dopant activation and damage removal. Samples were annealed by one of the following four methods; RTA(75$0^{\circ}C$/10s)+Ft FA+RTA(75$0^{\circ}C$/10s), RTA(100$0^{\circ}C$/10s)+FA, FA+The Ge Preamorphized sample exhibited a shallower junction depth than the non-preamorphized sample. When the employed RTA temperature was 100$0^{\circ}C$, FA+RTA annealing sequence exhibited better junction characteristics than RTA+FA thermal cycle from the viewpoint of junction depth, sheet resistance, $R_{s}$$.$ $x_{j}$, and leakage current.t.

70nm NMOSFET fabrication with ultra-shallow n+-p junctions using low energy As<+>(2) implantations (낮은 에너지의 As<+>(2) 이온 주입을 이용한 얕은 n+-p 접합을 가진 70nm NMOSFET의 제작)

  • Lee, Jong Deok;Lee, Byeong Guk
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.2
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    • pp.9-9
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    • 2001
  • Nano-scale의 게이트 길이를 가지는 MOSFET소자는 접합 깊이가 20∼30㎚정도로 매우 얕은 소스/드레인 확장 영역을 필요로 한다. 본 연구에서는 $As₂^ +$ 이온의 10keV이하의 낮은 에너지 이온 주입과 RTA(rapid thermal annealing)공정을 적용하여 20㎚이하의 얕은 접합 깊이와 1.O㏀/□ 이하의 낮은 면저항 값을 가지는 $n ^+$-p접합을 구현 하였다. 이렇게 형성된 $n^ +$-p 접합을 nano-scale MOSFET소자 제작에 적용 시켜서 70㎚의 게이트 길이를 가지는 NMOSFET을 제작하였다. 소스/드레인 확장 영역을 $As₂^ +$ 5keV의 이온 주입으로 형성한 100㎚의 게이트 길이를 가지는 NMOSFET의 경우, 60mV의 낮은 $V_ T$(문턱 전압감소) 와 87.2㎷의 DIBL (drain induced barrier lowering) 특성을 확인하였다. $10^20$$㎝^ -3$이상의 도핑 농도를 가진 abrupt한 20㎚급의 얕은 접합, 그리고 이러한 접합이 적용된 NMOSFET소자의 전기적 특성들은 As₂/sup +/의 낮은 에너지의 이온 주입 기술이 nano-scale NMOSFET소자 제작에 적용될 수 있다는 것을 제시한다.

NanoAnalysis with TOF-MEIS (TOF-MEIS 나노분석법)

  • Yu, Kyu-Sang;Moon, DaeWon
    • Vacuum Magazine
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    • v.2 no.2
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    • pp.17-23
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    • 2015
  • Medium Energy Ion Scattering (MEIS) has been successfully used for ultrathin film analysis such as gate oxides and multilayers due to its single atomic depth resolution in compostional and structural depth profiling. Recently, we developed a time-of-flight (TOF) MEIS for the first time, which can analyze a $10{\mu}m$ small spot. Small spot analysis would be useful for test pattern analysis in semiconductor industry and various thin film technology. The ion beam damage problem is minimized due to its improved collection efficiency by orders of magnitude and the ion beam neutralization problem is removed completely for quantitative analysis. Newly developed TOF-MEIS has been applied for gate oxides, ultra shallow junctions, nanoparticles, FINFET structures to provide compositional and structural profiles. Further development for submicron spot analysis and applications for functional nano thin films and nanostructured materials are expected for various nanotechnology and biotehnology.

Electrical Characteristics of Ultra-Shallow n+/p Junctions Formed by Using CoSi$_2$ as Diffusion Source of As (CoSi$_2$를 As의 확산원으로 형성한 매우 얇은 n+/p 접합의 전기적 특성)

  • 구본철;정연실;심현상;배규식
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1997.11a
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    • pp.242-245
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    • 1997
  • Co single layer and Co/Ti used to form a CoSi$_2$ contact. We fabricated the n+/p diodes with this CoSi$_2$ contact as diffusion source of As. The diodes wish CoSi$_2$ formed by Co/ri bilayer had more Bo7d electrical characteristics than CoSi$_2$ formed by Co single layer. This shows that the flatness of interface which is a parameters to affect the diodes\` electrical characteristics. And the electrical characteristics of diodes are more good when the second thermal activation processing temperature was low as much as 50$0^{\circ}C$ than the temperature high over than 80$0^{\circ}C$, it was thought as that the silicide was degradated at high temperature.

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70nm NMOSFET Fabrication with Ultra-shallow $n^{+}-{p}$ Junctions Using Low Energy $As_{2}^{+}$ Implantations (낮은 에너지의 $As_{2}^{+}$ 이온 주입을 이용한 얕은 $n^{+}-{p}$ 접합을 가진 70nm NMOSFET의 제작)

  • Choe, Byeong-Yong;Seong, Seok-Gang;Lee, Jong-Deok;Park, Byeong-Guk
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.2
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    • pp.95-102
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    • 2001
  • Nano-scale gate length MOSFET devices require extremely shallow source/drain eftension region with junction depth of 20∼30nm. In this work, 20nm $n^{+}$-p junctions that are realized by using this $As_{2}^{+}$ low energy ($\leq$10keV) implantation show the lower sheet resistance of the $1.0k\Omega$/$\square$ after rapid thermal annealing process. The $As_{2}^{+}$ implantation and RTA process make it possible to fabricate the nano-scale NMOSFET of gate length of 70nm. $As_{2}^{+}$ 5 keV NMOSFET shows a small threshold voltage roll-off of 60mV and a DIBL effect of 87.2mV at 100nm gate length devices. The electrical characteristics of the fabricated devices with the heavily doped and abrupt $n^{+}$-p junctions ($N_{D}$$10^{20}$$cm^{-3}$, $X_{j}$$\leq$20nm) suggest the feasibility of the nano-scale NMOSFET device fabrication using the $As_{2}^{+}$ low energy ion implantation.

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Cold Cathode using Avalanche Phenomenon at the Inversion Layer (반전층에서의 애벌런치 현상을 이용한 냉음극)

  • Lee, Jung-Yong
    • Journal of the Korean Vacuum Society
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    • v.16 no.6
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    • pp.414-423
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    • 2007
  • Field Emission Display(FED) has significant advantages over existing display technologies, particularly in the area of small and high quality display. In order to test the feasibility of fabricating the System-on-Chip(SOC) with FED, we conducted the experiment to use the p-n junction as an electron beam source for the flat panel display. A novel structure was constructed to form p-n junctions by generating inversion layer with the electric field from the cantilever style gate. When we applied more than 220V at the cantilever style gate which has a height of $1{\mu}m$, avalanche breakdown onset was successfully achieved. The characteristics was compared with the electron emission from the ultra shallow junction in the avalanche region. The experiment result and the future direction were discussed.

Nano Bio Imaging for NT and BT

  • Moon, DaeWon
    • Proceedings of the Korean Vacuum Society Conference
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    • 2015.08a
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    • pp.51.2-51.2
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    • 2015
  • Understanding interfacial phenomena has been one of the main research issues not only in semiconductors but only in life sciences. I have been trying to meet the atomic scale surface and interface analysis challenges from semiconductor industries and furthermore to extend the application scope to biomedical areas. Optical imaing has been most widely and successfully used for biomedical imaging but complementary ion beam imaging techniques based on mass spectrometry and ion scattering can provide more detailed molecular specific and nanoscale information In this presentation, I will review the 27 years history of medium energy ion scattering (MEIS) development at KRISS and DGIST for nanoanalysis. A electrostatic MEIS system constructed at KRISS after the FOM, Netherland design had been successfully applied for the gate oxide analysis and quantitative surface analysis. Recenlty, we developed time-of-flight (TOF) MEIS system, for the first time in the world. With TOF-MEIS, we reported quantitative compositional profiling with single atomic layer resolution for 0.5~3 nm CdSe/ZnS conjugated QDs and ultra shallow junctions and FINFET's of As implanted Si. With this new TOF-MEIS nano analysis technique, details of nano-structured materials could be measured quantitatively. Progresses in TOF-MEIS analysis in various nano & bio technology will be discussed. For last 10 years, I have been trying to develop multimodal nanobio imaging techniques for cardiovascular and brain tissues. Firstly, in atherosclerotic plaque imaging, using, coherent anti-stokes raman scattering (CARS) and time-of-flight secondary ion mass spectrometry (TOF-SIMS) multimodal analysis showed that increased cholesterol palmitate may contribute to the formation of a necrotic core by increasing cell death. Secondly, surface plasmon resonance imaging ellipsometry (SPRIE) was developed for cell biointerface imaging of cell adhesion, migration, and infiltration dynamics for HUVEC, CASMC, and T cells. Thirdly, we developed an ambient mass spectrometric imaging system for live cells and tissues. Preliminary results on mouse brain hippocampus and hypotahlamus will be presented. In conclusions, multimodal optical and mass spectrometric imaging privides overall structural and morphological information with complementary molecular specific information, which can be a useful methodology for biomedical studies. Future challenges in optical and mass spectrometric imaging for new biomedical applications will be discussed.

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