• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.11
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• pp.61-68
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• 2008

In this paper, we propose a RF front-end developments for vehicle UWB radar systems. UWB systems have a very narrow pulse width that is below 1ns. Therefore, UWB is designed to have broadband quality of low power several GHz and must coexist with the radio communication system. UWB's advantages include high channel capacity and data rate, because precise resolution for multi-path can easily position estimate and Rake receiver. Also, UWB has low interference because it displays broadband quality of low power. Positioning is made possible by short range accuracy, which can reduce the expense of system design. An RF front-end module is designed using the DCR(Direct ConveRsion) method and is composed in RF for vehicles at a low-cost.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.4
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• pp.745-752
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• 2005

In this paper we propose and implement a digital part of a receiver system for identifying a moving object and its tracking position in wireless environment. We assumed UWB(Ultra Wide Band)-based communication system for target application and used serial communication method(RS-232). The proposed digital receiver consists of RS-232-type1/RS-232-type2 for input and output of serial communication, ID Detector for detecting IDs, and PISO&Buffer circuit to buffer input signals for appropriate operation of ID Detector. We implemented the digital receiver with minimal hardware(H/W) resource according to target application of UWB-based communication system. So it correlates input patterns with pre-stored patterns though repeated detecting method for multiple IDs. Since it has reference panerns in the Ve-stored form, it can detect various IDs instantly. Also we can program content and size of reference patterns considering compatibility with other systems .The implemented H/W was mapped into XC2S100PQ208-5 FPGA of Xilinx, occupied 727($30\%$) cells, and stably operated in the clock frequency of 75MHz(13.341ns).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.2A
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• pp.121-129
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• 2008

This paper presents the spatial multiplexing MIMO system to increase data rate to double in MB-OFDM UWB system, which is ECMA standards, and compares BER performance of various receiver structures. The complexity and BER performance of various types of spatial multiplexing receivers are compared and analyzed using diagonal and horizontal encoding techniques for $2{\times}2$\;and\;2{\times}3$ antennas systems. Computer simulations exhibit that $2{\times}2$ MML and $2{\times}3$ ZF method show better BER performance than that of SISO system with simple complexity.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.12
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• pp.1297-1307
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• 2009

The purpose of this paper is to propose a detection algorithm and a tracking algorithm based on silent time using MB-OFDM UWB(Multi-Band Orthogonal Frequency Division Multiplexing Ultra Wide Band) receiver in order to satisfy DAA(Detect And Avoid) regulation of Korea to permit UWB in 3.1~4.8 GHz. In DAA regulation of Korea, if UWB device receives a signal more than -80 dBm/MHz from the victim system during UWB operation, the UWB system should avoid the collision within 2 sec. In this paper, we proposed the detection algorithm to detect the victim signal received by －80 dBm/MHz for the avoidance process that changes the operating UWB frequency to other UWB frequency and the subcarrier tracking algorithm to follow up the subcarrier positions of the victim signal for the tonenulling avoidance process that decreases the TX power of subcarriers occupied by the victim signal by -70 dBm/MHz. The performance of the detection algorithm and the tracking algorithm suggested in this paper is verified in simulation results considering various conditions.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.4
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• pp.238-246
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• 2011

A 3-5 GHz UWB radar chip in 0.13 ${\mu}m$ CMOS process is presented in this paper. The UWB radar transceiver for surveillance and biometric applications adopts the equivalent time sampling architecture and 4-channel time interleaved samplers to relax the impractical sampling frequency and enhance the overall scanning time. The RF front end (RFFE) includes the wideband LNA and 4-way RF power splitter, and the analog signal processing part consists of the high speed track & hold (T&H) / sample & hold (S&H) and integrator. The interleaved timing clocks are generated using a delay locked loop. The UWB transmitter employs the digitally synthesized topology. The measured NF of RFFE is 9.5 dB in 3-5 GHz. And DLL timing resolution is 50 ps. The measured spectrum of UWB transmitter shows the center frequency within 3-5 GHz satisfying the FCC spectrum mask. The power consumption of receiver and transmitter are 106.5 mW and 57 mW at 1.5 V supply, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.12
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• pp.1765-1767
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• 2016

Non-coherent UWB receivers are promising due to the low hardware complexity while the coherent receiver such as the rake receiver requires the complex hardware to estimate channel characteristics and get the synchronization. In this letter, the block coded modulation scheme as one of the most promising method is enhanced in terms of the performance. The performance enhancement is carried out by the modification of the block structure with unequal frame length for each pulse. Simulation results show that the proposed method has the performance enhancement by the transmission rate or bit error rate.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.8C
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• pp.806-813
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• 2009

This paper presents a modem chip design for high-speed wireless communications. Among the high-speed communication technologies, we design the UWB (Ultra-Wideband) modem SoC (System-on-Chip) Chip based on a MB-OFDM scheme which uses wide frequency band and gives low frequency interference to other communication services. The baseband system of the modem SoC chip is designed according to the standard document published by WiMedia. The SoC chip consists of FFT/IFFT (Fast Fourier Transform/Inverse Fast Fourier Transform), transmitter, receiver, symbol synchronizer, frequency offset estimator, Viterbi decoder, and other receiving parts. The chip is designed using 90nm CMOS (Complementary Metal-Oxide-Semiconductor) procedure. The chip size is about 5mm x 5mm and was fab-out in July 20th, 2009.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.309-310
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• 2008

In this paper, we propose a novel D-ATR (Differential-Average Transmitted Reference) scheme for UWB (Ultra Wide Band) based on impulse radio. The proposed scheme utilizing differential coding at transceiver, does not cause half loss of data rate unlike the conventional TR (Transmitted Reference) and ATR (Average TR) systems which transmit additional reference signals. In addition, the proposed scheme may provide improved BER (Bit Error Rate) performance by averaging the received reference signals like the conventional ATR. The proposed D-ATR receiver produces the averaged reference template by considering both the detected data bit and the differential coding rule.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.11A
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• pp.1086-1095
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• 2007

This paper proposes a novel non-coherent TOA estimation scheme using multiple correlation process on the existence of multiple simultaneously operating piconets (SOPs). Impulse radio-ultra wideband (IR-UWB) based on direct sequence spread spectrum (DSSS) using Gold sequence is employed in order to discriminate each piconet. In order to enhance the characteristic of correlation, this paper presents the method of multiple mask operation (MMO). The time of arrival (TOA) of direct line of sight (DLOS) path is estimated via two step coarse/fine timing detection. To verify the performance of proposed scheme, two distinct channel models approved by IEEE 802.15.4a Task Group (TG) are considered. According to the simulation results, it could conclude that the proposed scheme have performed better performance than the conventional method well even in densed indoor multi-path environment as well as in the existence of multiple SOPs.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.11 s.102
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• pp.1075-1085
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• 2005

The purpose of this paper is to design the architecture for synchronization of MB-OFDM UWB system that is being processed the standardization for Alt-PHY of WPAN(Wireless Personal Area Network) at IEEE802.15.3a and to analyze the implementation loss due to 4 parallel synchronization architecture for design or link margin. First an overview of the MB-OFDM UWB system based on IEEE802.15.3a Alt-PHY standard is described. The effects of non-ideal transmission conditions of the MB-OFDM UWB system including carrier frequency offset and sampling clock offset are analyzed to design a full digital architecture for synchronization. The synchronization architecture using 4-parallel structure is then proposed to consider the VLSI implementation including algorithms for carrier frequency offset and sampling clock offset to minimize the effects of synchronization errors. The overall performance degradation due to the proposed synchronization architecture is simulated to be with maximum 3.08 dB of the ideal receiver in maximum carrier frequency offset and sampling clock offset tolerance fir MB-OFDM UWB system.