• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.376-377
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• 2006

Chemical Mechanical Planarization (CMP) has emerged as an enabling technology for the manufacturing of multi-level metal interconnects used in high-density Integrated Circuits (IC). Recently, multi-level structures have been also widely used m the MEMS device such as micro engines, pressure sensors, micromechanical fluid pumps, micro mirrors and micro lenses. Especially, among the thin films available in IC technologies, polysilicon has probably found the widest range of uses in silicon technology based MEMS. This paper presents the characteristic of polysilicon CMP for multi-level MEMS structures. Two-step CMP process verifies that is possible to decrease dishing amount with two type of slurries characteristics. This approach is attractive because two-step CMP process can be decreased dishing amount considerably more then just one CMP process.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 추계학술대회 논문집 Vol.15
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• pp.39-42
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• 2002

Recently, CMP (chemical mechanical polishing) technology has been widely used for global planarization of multi-level interconnection for ULSI applications. However, COO (cost of ownership) and COC (cost of consumables) were relatively increased because of expensive slurry. In this paper, we have studied the possibility of recycle of reused silica slurry in order to reduce the costs of CMP slurry. The post-CMP thickness and within-wafer non-uniformity(WIWNU) were measured as a function of different slurry composition. As a experimental result, the performance of reused slurry with annealed silica abrasive of 2 wt% contents was showed high removal rate and low non-uniformity. Therefore, we propose two-step CMP process as follows In the first-step CMP, we can polish the thick and rough film surface using remaked slurry, and then, in the second-step CMP, we can polish the thin film and fine pattern using original slurry. In summary, we can expect the saving of high costs of slurry.

• 한국전기전자재료학회논문지
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• 제16권9호
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• pp.759-764
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• 2003

Recently, CMP (chemical mechanical polishing) technology has been widely used for global planarization of multi-level interconnection for ULSI applications. However, COO (cost of ownership) and COC (cost of consumables) were relatively increased because of expensive slurry. In this paper, we have studied the possibility of recycle of roused silica slurry in order to reduce the costs of CMP slurry. The post-CMP thickness and within-wafer non-uniformity (WIWNU) wore measured as a function of different slurry composition. As an experimental result, the performance of reused slurry with annealed silica abrasive of 2 wt％ contents was showed high removal rate and low non-uniformity. Therefore, we propose two-step CMP process as follows , In tile first-step CMP, we can polish the thick and rough film surface using remaked slurry, and then, in the second-step CMP, we can polish the thin film and fine pattern using original slurry. In summary, we can expect the saying of high costs of slurry.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.525-526
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• 2007

Over-polishing is required to completely remove the material of top surface across whole wafer, in spite of a local dishing problem. This paper introduces the two-step CMP process using protective layer and high selectivity slurry, to reduce dishing amount and variation. The 30nm thick protective oxide layer was deposited on the pattern, and then polished with low selectivity slurry to partially remove the projected area while suppressing the removal rate of the recessed area. After the first step CMP process, high selectivity slurry was used to minimize the dishing amount and variation in pattern structure. Experimental result shows that two-step CMP process can be successfully applicable to reduce the dishing defect generated in over-polishing.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.523-524
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• 2007

This paper discusses the planarization process of thick copper film structure used for power supply device. Chemical mechanical polishing(CMP) has been used to remove a metal film and obtain a surface planarization which is essential for the semiconductor devices. For the thick metal removal, however, the long process time and other problems such as dishing, delamination and metal layer peeling are being issued, Compared to the traditional CMP process, Electro-chemical mechanical planarization(ECMP) is suggested to solve these problems. The two-step process composed of the ECMP and the conventional CMP is used for this experiment. The first step is the removal of several tens ${\mu}m$ of bulk copper on patterned wafer with ECMP process. The second step is the removal of residual copper layer aimed at a surface planarization. For more objective comparison, the traditional CMP was also performed. As an experimental result, total process time and process defects are extremely reduced by the two-step process.

• 한국전기전자재료학회논문지
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• 제13권7호
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• pp.568-574
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• 2000

We have been optimized tungsten(W) plug CMP(chemical mechanical polishing) characteristics using two different kinds of component of slurry and two different kinds of pad which have different hardness. The comparison of oxide film roughness on around W plug after polishing has been carried out. And W plug recess for consumable sets and dishing effect at dense area according to the rate of over-polishing has been investigated. Also the analysis of residue on surface after cleaning have been performed. As a experimental result we have concluded that the consumable set of slurry A and hard pad was good for W plug CMP process. After decreasing the rate of chemical reaction of silica slurry and adding two step buffering we could reduce the expanding of W plug void however we are still recognizing to need a more development for those kinds of CMP consumables.

• 멤브레인
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• 제6권2호
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• pp.72-78
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• 1996

양이온성의 quaternary ammonium polysulfone인 AMPS는 2단계 과정을 통하여 제조하였다. 먼저, 폴리술폰을 chloromethyl methyl ether와 촉매로 ZnO를 사용하여 chloromethylation반응으로 CMPS를 제조하는 단계와 준비된 CMPS에 triethylamine을 반응시켜 quaternary ammonium기를 도입시키는 amination 단계로 이루어 진다.

• 마이크로전자및패키징학회지
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• 제20권2호
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• pp.47-51
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• 2013

본 연구에서는 웨이퍼 레벨 Cu 본딩을 이용한 3D 적층 IC의 개발을 위해 2단계 기계적 화학적 연마법(CMP)을 제안하고 그 결과를 고찰하였다. 다마신(damascene) 공정을 이용한 $Cu/SiO_2$ 복합 계면에서의 Cu dishing을 최소화하기 위해 Cu CMP 후 $SiO_2$ CMP를 추가로 시행하였으며, 이를 통해 Cu dishing을 $100{\sim}200{\AA}$까지 낮출 수 있었다. Cu 범프의 표면거칠기도 동시에 개선되었음을 AFM 관찰을 통해 확인하였다. 2단 CMP를 적용하여 진행한 웨이퍼 레벨 Cu 본딩에서는 dishing이나 접합 계면이 관찰되지 않아 2단 CMP 공정이 성공적으로 적용되었음을 확인할 수 있었다.

• Transactions on Electrical and Electronic Materials
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• 제7권4호
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• pp.157-162
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• 2006

Chemical-mechanical polishing (CMP), one of the dominant technology for ULSI planarization, is used to flatten the micro electro-mechanical systems (MEMS) structures. The objective of this paper is to achieve good planarization of the deposited film and to improve deposition efficiency of subsequent layer structures by using surface-micromachining process in MEMS technology. Planarization characteristic of poly-Si film deposited on thin oxide layer with MEMS structures is evaluated with different slurries. Patterns used for this research have shapes of square, density, line, hole, pillar, and micro engine part. Advantages of CMP process for MEMS structures are observed respectively by using the test patterns with structures larger than 1 urn line width. Preliminary tests for material selectivity of poly-Si and oxide are conducted with two types of silica slurries: $ILD1300^{TM}\;and\;Nalco2371^{TM}$. And then, the experiments were conducted based on the pretest. A selectivity and pH adjustment of slurry affected largely step heights of MEMS structures. These results would be anticipated as an important bridge stone to manufacture MEMS CMP slurry.

• 자원환경지질
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• 제32권5호
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• pp.495-502
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• 1999

Common-mid-point (CMP) seismic data on a dipping layer have have a stacking different from a horizontal layer velocity and the reflection points on data are dispersed to many positions. Therefore, the CMP data are not stacked well by the conventional stacking method using the horizontal layer velocity. The CMP gather can ideally stacked by applying dip-moveout(DMO) processing. Hence, modern seismic processing indludes DMO as an essential routine step. DMO processing techniques are broadly categorized by two, Fourier transform and integral methods, each of which has many different computational schemes. In this study, the dip-decomposition technique of the Fourier transform method is used to test the DMO effect on the synthetic scismic data generated for dipping structures. Each of constnat offset sections NMO corrected by using the layer velocity of the model and DMO processed. The resulting zero-offset sections for many offsets are stacked. The stacked sections with DMO processing show the structural boundaries of the models much better than those without DMO processing.