• 전자공학회논문지A
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• 제33A권6호
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• pp.230-238
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• 1996

In this paper, digital corrction and calibration circuit for a high-resolution CMOS pipelined A/D converter are proposed. The circuits were actually applied to a 12 -bit 4-stage pipelined A/D converter which was implemented in a 0.8${\mu}$m p-well CMOS process. The proposed digital correction logic is based on optimum multiplexer and two nonoverlapping clock phases resulting in a small die area snd a modular pipelined architecture. The propsoed digital calibration logic which consists of calibration control logic, error averaging logic, and memory can effectively perform self-calibration with little modifying analog functional bolcks of a conventional pipelined A/D conveter.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(5)
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• pp.191-194
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• 2000

A 2.4 GHz single ended two stage low noise amplifier(LNA) is designed for Bluetooth application. The circuit was implemented in a standard digital 0.25 $\mu\textrm{m}$ CMOS process with one poly and five metal layers. At 2.4 GHz, the LNA dissipates 34.5 mW from a 2.5V power supply voltage and provides 24.6 dB power gain, 2.85 dB minimum noise figure, -66.3 dB reverse isolation, and an output 1-dB compression level of 8.5 dBm.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권1호
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• pp.59-64
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• 2011

A low noise and low power RF front-end for 5.8 GHz DSRC (Dedicated Short Range Communication) receiver is presented. The RF front-end is composed of a single-to-differential two-stage LNA and a Gilbert down-conversion mixer. In order to remove an external balun and 5.8 GHz LC load tuning circuit, a single-to-differential LNA with capacitive cross coupled pair is proposed. The RF front-end is fabricated in a 0.13 ${\mu}m$ CMOS process and draws 7.3 mA from a 1.2 V supply voltage. It shows a voltage gain of 40 dB and a noise figure (NF) lower than 4.5 dB over the entire DSRC band.

• 한국통신학회논문지
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• 제15권2호
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• pp.147-154
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• 1990

갈륨비소를 사용한 SCFL을 채택하여 4:1 시분할 멀티플랙서를 설계하였다. 설계된 멀티플렉서는 2:1 시분할 주파수 분할기를 사용하여 2:1 멀티플렉서 2단을 사용하였다. 시뮬레이션 결과, 최고 동작 주파수는 6.25GHz이었고 전력소모는 192mW이었다. 따라서 최대 출력 bit율은 12.5Gbit/sec를 얻었다. 이 결과 기존의 멀티플렉서에 비해 속도 및 전력소모 면에서 상당히 개선된 것이다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2008년도 추계학술대회 논문집
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• pp.150-153
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• 2008

This paper presents soft-switching boost converter adding to auxiliary switch and resonant circuit in conventional boost converter. This approach features a two power stage which implements both conventional BLDC motor speed control and input power factor correction. This converter is especially useful in application such as home appliance. Theoretical analysis and simulation results are presented.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.299-299
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• 2007

This paper presents an omni-directional piezoelectric actuator which utilizes only one actuator. The actuator has a simple structure of cone type consists of two piezoelectric ceramics of ring type and electrodes divided four segments and a stainless steel body. To find the optimal operating condition of the actuator, the frequency characteristics of the actuator are analyzed by ATILA, FEM and measured by Impedance Analyzer. We have also developed a stage using the omni-directional actuator and an actuator driver circuit to create four sinusoidal waves with a variable frequency and phase difference.

• 한국멀티미디어학회논문지
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• 제11권6호
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• pp.816-827
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• 2008

In this paper, two-stage pipelined floating-point arithmetic unit (FP-AU) is designed. The FP-AU processor supports seventeen operations to apply 3D graphics processor and has area-efficient and low-latency architecture that makes use of modified dual-path computation scheme, new normalization circuit, and modified compound adder based on flagged prefix adder. The FP-AU has about 4-ns delay time at logic synthesis condition using $0.18{\mu}m$ CMOS standard cell library and consists of about 5,930 gates. Because it has 250 MFLOPS execution rate and supports saturated arithmetic including a number of graphics-oriented operations, it is applicable to mobile 3D graphics accelerator efficiently.

• Journal of Multimedia Information System
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• 제6권1호
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• pp.7-14
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• 2019

This work presents a virtual prototyping design approach for an area-based image stitching hardware. The virtual hardware obtained from virtual prototyping is equivalent to the conceptual algorithm, yet the conceptual blocks are linked to the actual circuit components including the memory, logic gates, and arithmetic units. Through the proposed method, the overall structure, size, and computation speed of the actual hardware can be estimated in the early design stage. As a result, the optimized virtual hardware facilitates the hardware implementation by eliminating trail design and redundant simulation steps to optimize the hardware performance. In order to verify the feasibility of the proposed method, the virtual hardware of an image stitching platform has been realized, where it required 10,522,368 clock cycles to stitch two $1280{\times}1024$ sized images. Furthermore, with a clock frequency of 250MHz, the estimated computation time of the proposed virtual hardware is 0.877sec, which is 10x faster than the software-based image stitch platform using MATLAB.

• Journal of Electrical Engineering and Technology
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• 제3권3호
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• pp.391-400
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• 2008

Multi-pulse topology of converters using elementary six-pulse GTO - VSC (gate turn off based voltage source converter) operated under fundamental frequency switching (FFS) control is widely adopted in high power rating static synchronous compensators (STATCOM). Practically, a 48-pulse ($6{\times}8$ pulse) configuration is used with the phase angle control algorithm employing proportional and integral (PI) control methodology. These kinds of controllers, for example the ${\pm}80MVAR$ compensator at Inuyama switching station, KEPCO, Japan, employs two stages of magnetics viz. intermediate transformers (as many as VSCs) and a main coupling transformer to minimize harmonics distortion in the line and to achieve a desired operational efficiency. The magnetic circuit needs altogether nine transformers of which eight are phase shifting transformers (PST) used in the intermediate stage, each rating equal to or more than one eighth of the compensator rating, and the other one is the main coupling transformer having a power rating equal to that of the compensator. In this paper, a two-level 48-pulse ${\pm}100MVAR$ STATCOM is proposed where eight, six-pulse GTO-VSC are employed and magnetics is simplified to single-stage using four transformers of which three are PSTs and the other is a normal transformer. Thus, it reduces the magnetics to half of the value needed in the commercially available compensator. By adopting the simple PI-controllers, the model is simulated in a MATLAB environment by SimPowerSystems toolbox for voltage regulation in the transmission system. The simulation results show that the THD levels in line voltage and current are well below the limiting values specified in the IEEE Std 519-1992 for harmonic control in electrical power systems. The controller performance is observed reasonably well during capacitive and inductive modes of operation.

• 한국산학기술학회논문지
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• 제13권4호
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• pp.1789-1796
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• 2012

본 논문에서는 RFID 태그 칩 구동을 위한 새로운 고효율 CMOS 브리지 정류기를 설계하고 해석하였다. 동작 주파수가 높아짐에 따라 증가하는 게이트 누설전류의 주 통로가 되는 게이트 커패시턴스를 회로적인 방법으로 감소시키기 위해 제안한 정류기의 입력단을 두 개의 NMOS로 종속접속형으로 연결하여 설계하였으며, 이러한 종속접속형 입력단을 이용한 게이트 커패시턴스 감소 기법을 이론적으로 제시하였다. 또한 제안한 정류기의 출력특성은 고주파 소신호 등가회로를 이용하여 해석적으로 유도하였다. 일반적인 경우의 $50K{\Omega}$ 부하저항에 대해, 제안한 정류기는 915MHz의 UHF(for ISO 18000-6)에서는 28.9%, 2.45GHz의 마이크로파 대역 (for ISO 18000-4)에서는 15.3%의 전력변환효율을 보여, 915MHz에서 26.3%와 26.8%, 2.45GHz에서 13.2%와 12.6%의 전력변환효율을 보인 비교된 기존의 두 정류기에 비해 보다 개선된 전력변환효율을 보였다. 따라서 제안한 정류기는 다양한 종류의 RFID 시스템의 태그 칩 구동을 위한 범용 정류기로 사용될 수 있을 것이다.